Altera Arria 10 Avalon-MM User Manual
Page 89
Byte Offset
Register
Dir
Description
14'h3C10
cfg_prm_cmd[15:0]
O
Base/Primary Command register for the PCI
Configuration Space.
14'h3C14
cfg_root_ctrl[7:0]
O
Root control and status register of the PCI-Express
capability. This register is only available in Root
Port mode.
14'h3C18
cfg_sec_ctrl[15:0]
O
Secondary bus Control and Status register of the
PCI-Express capability. This register is only
available in Root Port mode.
14'h3C1C
cfg_secbus[7:0]
O
Secondary bus number. Available in Root Port
mode.
14'h3C20
cfg_subbus[7:0]
O
Subordinate bus number. Available in Root Port
mode.
14'h3C24
cfg_msi_addr_low[31:0]
O
cfg_msi_add[31:0]
is the MSI message address.
14'h3C28
cfg_msi_addr_hi[63:32]
O
cfg_msi_add[63:32]
is the MSI upper message
address.
14'h3C2C
cfg_io_bas[19:0]
O
The IO base register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h3C30
cfg_io_lim[19:0]
O
The IO limit register of the Type1 Configuration
Space. This register is only available in Root Port
mode.
14'h3C34
cfg_np_bas[11:0]
O
The non-prefetchable memory base register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C38
cfg_np_lim[11:0]
O
The non-prefetchable memory limit register of the
Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C3C
cfg_pr_bas_low[31:0]
O
The lower 32 bits of the prefetchable base register of
the Type1 Configuration Space. This register is only
available in Root Port mode.
14'h3C40
cfg_pr_bas_hi[43:32]
O
The upper 12 bits of the prefetchable base registers
of the Type1 Configuration Space. This register is
only available in Root Port mode.
UG-01145_avmm
2015.05.14
Control Register Access (CRA) Avalon-MM Slave Port
6-23
Registers
Altera Corporation