Altera Arria 10 Avalon-MM - Manual (Page 49)

Figure 5-1: Signals in 64- or 128-Bit Avalon-MM Interface to the Application Layer
tx_out0[-1:0]
rx_in0[-1:0]
1-Bit Serial 32-Bit
Avalon-MM
CRA
Slave Port
(Optional,
Not available for
Completer-Only
Single Dword)
64- or 128-Bit
Avalon-MM TX
Slave Port
(Not used for
Completer-Only)
Test
Interface
test_in[31:0]
64- or 128-Bit
Avalon-MM RX
Master Port
Clocks
npor
nreset_status
pin_perst
Reset &
Lock Status
refclk
coreclkout_hip
cra_readdata[31:0]
cra_waitrequest
cra_byteenable[3:0]
cra_chipselect
cra_address[14:0]
cra_read
cra_write
cra_writedata[31:0]
txs_writedata[63:0] or [127:0]
txs_busrtcount[6:0]
txs_chipselect
txs_read
txs_write
txs_address[-1:0]
txs_byteenable[-1:0]
txs_readdatavalid
txs_readdata[63:0] or [127:0]
txs_waitrequest
rxm_bar0_write_
rxm_bar0_address_[31:0]
rxm_bar0_writedata_[-1:0]
rxm_bar0_byteenable_[7:0]
rxm_bar0_burstcount_[6:0]
rxm_bar0_waitrequest_
rxm_bar0_read_
rxm_bar0_readdata_[-1:0]
rxm_bar0_readdatavalid
rxm_irq[:0], < 16
cra_irq_irq
64- or 128-Bit Avalon-MM Interface to
Application Layer
Hard IP
Reconfiguration
(Optional)
hip_reconfig_clk
hip_reconfig_rst_n
hip_reconfig_address[9:0]
hip_reconfig_read
hip_reconfig_readdata[15:0]
hip_reconfig_write
hip_reconfig_writedata[15:0]
hip_reconfig_byte_en[1:0]
ser_shift_load
interface_sel
MsiIntfc_o[81:0]
MsiControl_o[15:0]
MsixIntfc_o[15:0]
IntxReq_i
IntxAck_o
Multiple
MSI/MSI-X
txdata0[31:0]
txdatak0[3:0]
txblkst0
rxdata0[31:0]
rxdatak0[3:0]
rxblkst0
txdetectrx0
txelecidle0
txcompl0
rxpolarity0
powerdown0[1:0]
currentcoeff0[17:0]
currentrxpreset0[2:0]
txmargin[2:0]
txswing
txsynchd0[1:0]
rxsyncd[1:0]
rxvalid0
phystatus0
rxelecidle0
rxstatus0[2:0]
simu_mode_pipe
sim_pipe_rate[1:0]
sim_pipe_pclk_in
sim_pipe_pclk_out
sim_pipe_clk250_out
sim_pipe_clk500_out
sim_ltssmstate[4:0]
rxfreqlocked0
rxdataskip0
txdataskip0
eidleinfersel0[2:0]
txdeemph0
Transmit Data
Interface Signals
Receive Data
Interface Signals
Command
Interface Signals
Status
Interface Signals
PIPE
Interface
for Simulation
and Hardware
Debug Using
dl_ltssm[4:0]
SignalTap,
Gen3 version
Note: Signals listed for BAR0 are the same as those for BAR1–BAR5 when those BARs are enabled in the
parameter editor.
Variations using the Avalon-MM interface implement the Avalon-MM protocol described in the Avalon
Interface Specifications. Refer to this specification for information about the Avalon-MM protocol,
including timing diagrams.
Related Information
Avalon Interface Specifications
5-2 64- or 128-Bit Avalon-MM Interface to the Application Layer
UG-01145_avmm
2015.05.14
Altera Corporation 64- or 128-Bit Avalon-MM Interface to the Application Layer
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