Altera Arria 10 Avalon-MM - Manual (Page 207)

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2015.05.14
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Revision History for the Avalon-MM Interface
Date Version Changes Made
2015.05.14 15.0 Made the following changes to the user guide:
• Added Enable Hard IP Status Bus when using the AVMM
interface parameter in Interface System Settings on page 3-4.
This parameter is available in the IP core v15.0 and later.
2015.05.04 15.0 Made the following changes to the user guide:
• Enhanced the descriptions in
Avalon-MM-to-PCI Express
Address Translation Table on page 6-18.
• Added Enable Altera Debug Master Endpoint (ADME)
parameter to support optional Native PHY register programming
with the Altera System Console.
• Added support to send message TLPs with data payload of any
length from a Root Port. Refer to Programming Model for
Avalon-MM Root Port on page 6-26 and to the new supported
TLP entry for Avalon-MM variations in the Feature Comparison
for all Hard IP for PCI Express IP Cores table in Features .
• Added information about the new custom example designs, in
Example Designs on page 1-9.
• Added column for Avalon-ST Interface with SR-IOV variations in
Feature Comparison for all Hard IP for PCI Express IP Cores
table in Features section.
• Enhanced descriptions of channel placement, added fPLL
placement for Gen1 and Gen2 data rates, and added master CGB
location, in Physical Layout of Hard IP In Arria 10 Devices on
page 4-1.
• Updated DUT module name in testbench and example design
figures.
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