Altera Arria 10 Avalon-MM - Manual (Page 106)

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip
×4 Gen3 256 125 MHz
×8 Gen3 256 250 MHz
pld_clk
coreclkout_hip
can drive the Application Layer clock along with the
pld_clk
input to the IP core. The
pld_clk
can optionally be sourced by a different clock than
coreclkout_hip
. The
pld_clk
minimum
frequency cannot be lower than the
coreclkout_hip
frequency. Based on specific Application Layer
constraints, a PLL can be used to derive the desired frequency.
Clock Summary
Table 7-2: Clock Summary
Name Frequency Clock Domain
coreclkout_hip 62.5, 125 or 250 MHz Avalon-ST interface between the Transaction and
Application Layers.
pld_clk 62.5, 125, or 250 MHz Application and Transaction Layers.
refclk
100 MHz SERDES (transceiver). Dedicated free running input
clock to the SERDES block.
7-6 pld_clk
UG-01145_avmm
2015.05.14
Altera Corporation Arria 10 Reset and Clocks
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