Altera Arria 10 Avalon-MM User Manual
Page 134
Figure 10-6: Qsys System for PCI Express with Poor Address Space Utilization
The following figure uses a filter to hide the Conduit interfaces that are not relevant in this discussion.
Figure 10-7: Poor Address Map
The following figure illustrates the address map for this system.
The auto-assigned base addresses result in the following three large BARs:
• BAR0 is 28 bits. This is the optimal size because it addresses the Offchip_Data_Mem which requires
28 address bits.
• BAR2 is 29 bits. BAR2 addresses the Quick_Data_Mem which is 4 KBytes;. It should only require 12
address bits; however, it is consuming 512 MBytes of address space.
• BAR4 is also 29 bits. BAR4 address PCIe Cra is 16 KBytes. It should only require 14 address bits;
however, it is also consuming 512 MBytes of address space.
10-16
Minimizing BAR Sizes and the PCIe Address Space
UG-01145_avmm
2015.05.14
Altera Corporation
IP Core Architecture
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)