Altera Arria 10 Avalon-MM User Manual
Page 11

Transaction Layer
Packet type (TLP)
(transmit support)
Avalon-ST Interface
Avalon-MM
Interface
Avalon-MM DMA
Avalon-ST Interface with SR-
IOV
Memory Read
Lock Request
(
MRdLk
)
EP/RP
EP
EP
Memory Write
Request (
MWr
)
EP/RP
EP/RP
EP
EP
I/O Read
Request (
IORd
)
EP/RP
EP/RP
EP
I/O Write
Request (
IOWr
)
EP/RP
EP/RP
EP
Config Type 0
Read Request
(
CfgRd0
)
RP
RP
EP
Config Type 0
Write Request
(
CfgWr0
)
RP
RP
EP
Config Type 1
Read Request
(
CfgRd1
)
RP
RP
EP
Config Type 1
Write Request
(
CfgWr1
)
RP
RP
EP
Message
Request (
Msg
)
EP/RP
EP/RP
EP
Message
Request with
Data (
MsgD
)
EP/RP
EP/RP
EP
Completion
(
Cpl
)
EP/RP
EP/RP
EP
EP
Completion
with Data
(
CplD
)
EP/RP
EP
EP
Completion-
Locked (
CplLk
)
EP/RP
EP
Completion
Lock with Data
(
CplDLk
)
EP/RP
EP
UG-01145_avmm
2015.05.14
Features
1-5
Datasheet
Altera Corporation
                    See also other documents in the category Altera Measuring instruments:                                                            
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 - MAX 10 Power (21 pages)
 - Unique Chip ID (12 pages)
 - Remote Update IP Core (43 pages)
 - Device-Specific Power Delivery Network (28 pages)
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 - Hybrid Memory Cube Controller (69 pages)
 - ALTDQ_DQS IP (117 pages)
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 - MAX 10 Embedded Multipliers (37 pages)
 - MAX 10 Clocking and PLL (86 pages)
 - MAX 10 FPGA (26 pages)
 - MAX 10 FPGA (56 pages)
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 - GPIO (22 pages)
 - LVDS SERDES (27 pages)
 - User Flash Memory (33 pages)
 - ALTDQ_DQS2 (100 pages)
 - Avalon Tri-State Conduit Components (18 pages)
 - Cyclone V Avalon-MM (166 pages)
 - Cyclone III FPGA Starter Kit (36 pages)
 - Cyclone V Avalon-ST (248 pages)
 - Stratix V Avalon-ST (286 pages)
 - Stratix V Avalon-ST (293 pages)
 - DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
 - Arria 10 Avalon-ST (275 pages)
 - Avalon Verification IP Suite (224 pages)
 - Avalon Verification IP Suite (178 pages)
 - FFT MegaCore Function (50 pages)
 - DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
 - Floating-Point (157 pages)
 - Integer Arithmetic IP (157 pages)
 - Embedded Peripherals IP (336 pages)
 - JESD204B IP (158 pages)
 - Low Latency Ethernet 10G MAC (109 pages)
 - LVDS SERDES Transmitter / Receiver (72 pages)
 - Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
 - Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
 - IP Compiler for PCI Express (372 pages)
 - Parallel Flash Loader IP (57 pages)
 - Nios II C2H Compiler (138 pages)
 - RAM-Based Shift Register (26 pages)
 - RAM Initializer (36 pages)
 - Phase-Locked Loop Reconfiguration IP Core (51 pages)
 - DCFIFO (28 pages)
 
