Altera Arria 10 Avalon-MM - Manual (Page 88)

Address Name Access
Mode
Description
0x3B14 P2A_MAILBOX5 RO PCI Express-to-Avalon-MM mailbox 5
0x3B18 P2A_MAILBOX6 RO PCI Express-to-Avalon-MM mailbox 6
0x3B1C P2A_MAILBOX7 RO PCI Express-to-Avalon-MM mailbox 7
Control Register Access (CRA) Avalon-MM Slave Port
Table 6-23: Configuration Space Register Descriptions
For registers that are less than 32 bits, the upper bits are unused.
Byte Offset
Register Dir Description
14'h3C00
cfg_dev_ctrl[15:0] O
cfg_devctrl[15:0]
is device control for the PCI
Express capability structure.
14'h3C04
cfg_dev_ctrl2[15:0] O
cfg_dev2ctrl[15:0]
is device control 2 for the
PCI Express capability structure.
14'h3C08
cfg_link_ctrl[15:0] O
cfg_link_ctrl[15:0]
is the primary Link Control
of the PCI Express capability structure.
For Gen2 or Gen3 operation, you must write a 1’b1
to Retrain Link bit (Bit[5] of the
cfg_link_ctrl)
of
the Root Port to initiate retraining to a higher data
rate after the initial link training to Gen1 L0 state.
Retraining directs the LTSSM to the Recovery state.
Retraining to a higher data rate is not automatic for
the Arria 10 Hard IP for PCI Express IP Core even
if both devices on the link are capable of a higher
data rate.
14'h3C0C
cfg_link_ctrl2[15:0] O
cfg_link_ctrl2[31:16]
is the secondary Link
Control register of the PCI Express capability
structure for Gen2 operation.
When
tl_cfg_addr=2
,
tl_cfg_ctl
returns the
primary and secondary Link Control registers,
{cfg_link_ctrl[15:0], cfg_link_
ctrl2[15:0]}
, the primary Link Status register
contents is available on
tl_cfg_sts[46:31]
.
For Gen1 variants, the link bandwidth notification
bit is always set to 0. For Gen2 variants, this bit is
set to 1.
6-22 Control Register Access (CRA) Avalon-MM Slave Port
UG-01145_avmm
2015.05.14
Altera Corporation Registers
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