Altera Arria 10 Avalon-MM Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for Arria 10 Avalon-MM Altera
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 212 |
| Size: | 1.84 MB |
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Document Outline
- Arria 10 Avalon-MM Interface for PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
- Running Qsys
- Generating the Example Design
- Understanding Simulation Log File Generation
- Running a Gate-Level Simulation
- Simulating the Single DWord Design
- Generating Quartus II Synthesis Files
- Creating a Quartus II Project
- Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
- Compiling the Design
- Programming a Device
- Understanding Channel Placement Guidelines
- 3. Parameter Settings
- 4. Physical Layout of Hard IP In Arria 10 Devices
- 5. 64- or 128-Bit Avalon-MM Interface to the Application Layer
- 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals
- RX Avalon-MM Master Signals
- 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
- Clock Signals
- Reset
- Interrupts for Endpoints when Multiple MSI/MSI‑X Support Is Enabled
- Hard IP Reconfiguration Interface
- Physical Layer Interface Signals
- 6. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- Type 1 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- 64- or 128-Bit Avalon-MM Bridge Register Descriptions
- Avalon-MM to PCI Express Interrupt Registers
- Avalon-MM to PCI Express Interrupt Status Registers
- Avalon-MM to PCI Express Interrupt Enable Registers
- PCI Express Mailbox Registers
- Avalon-MM-to-PCI Express Address Translation Table
- PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
- Avalon-MM Mailbox Registers
- Control Register Access (CRA) Avalon-MM Slave Port
- Avalon-MM to PCI Express Interrupt Registers
- Programming Model for Avalon-MM Root Port
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- 7. Arria 10 Reset and Clocks
- 8. Interrupts for Endpoints
- 9. Error Handling
- 10. IP Core Architecture
- Top-Level Interfaces
- Avalon-MM Interface
- Clocks and Reset
- Interrupts
- PIPE
- Data Link Layer
- Physical Layer
- 32-Bit PCI Express Avalon-MM Bridge
- Avalon‑MM Bridge TLPs
- Avalon-MM-to-PCI Express Write Requests
- Avalon-MM-to-PCI Express Upstream Read Requests
- PCI Express-to-Avalon-MM Read Completions
- PCI Express-to-Avalon-MM Downstream Write Requests
- PCI Express-to-Avalon-MM Downstream Read Requests
- Avalon-MM-to-PCI Express Read Completions
- PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
- Minimizing BAR Sizes and the PCIe Address Space
- Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
- Completer Only Single Dword Endpoint
- 11. Design Implementation
- 12. Throughput Optimization
- 13. Optional Features
- 14. Avalon-MM Testbench and Design Example
- Arria 10 Avalon-MM Endpoint Testbench
- Arria 10 Avalon-MM Root Port Testbench
- Endpoint Design Example
- Avalon-MM Test Driver Module
- DMA Write Cycles
- DMA Read Cycles
- Avalon-MM Root Port Design Example
- Root Port BFM
- BFM Procedures and Functions
- ebfm_barwr Procedure
- ebfm_barwr_imm Procedure
- ebfm_barrd_wait Procedure
- ebfm_barrd_nowt Procedure
- ebfm_cfgwr_imm_wait Procedure
- ebfm_cfgwr_imm_nowt Procedure
- ebfm_cfgrd_wait Procedure
- ebfm_cfgrd_nowt Procedure
- BFM Configuration Procedures
- BFM Shared Memory Access Procedures
- BFM Log and Message Procedures
- Verilog HDL Formatting Functions
- Procedures and Functions Specific to the Chaining DMA Design Example
- Setting Up Simulation
- 15. Debugging
- A. Frequently Asked Questions
- B. Lane Initialization and Reversal
- C. Additional Information