Altera Arria 10 Avalon-MM - Manual (Page 86)

Bits Name Access Description
[15:2] Reserved — —
[16] P2A_MAILBOX_INT0 RW1C 1 when the P2A_MAILBOX0 is written
[17] P2A_MAILBOX_INT1 RW1C 1 when the P2A_MAILBOX1 is written
[18] P2A_MAILBOX_INT2 RW1C 1 when the P2A_MAILBOX2 is written
[19] P2A_MAILBOX_INT3 RW1C 1 when the P2A_MAILBOX3 is written
[20] P2A_MAILBOX_INT4 RW1C 1 when the P2A_MAILBOX4 is written
[21] P2A_MAILBOX_INT5 RW1C 1 when the P2A_MAILBOX5 is written
[22] P2A_MAILBOX_INT6 RW1C 1 when the P2A_MAILBOX6 is written
[23] P2A_MAILBOX_INT7 RW1C 1 when the P2A_MAILBOX7 is written
[31:24] Reserved — —
An Avalon-MM interrupt can be asserted for any of the conditions noted in the
Avalon-MM Interrupt
Status
register by setting the corresponding bits in the
PCI Express to Avalon-MM Interrupt Enable
register.
PCI Express interrupts can also be enabled for all of the error conditions described. However, it is likely
that only one of the Avalon-MM or PCI Express interrupts can be enabled for any given bit. Typically, a
single process in either the PCI Express or Avalon-MM domain handles the condition reported by the
interrupt.
Table 6-20: INT‑X Interrupt Enable Register for Endpoints, 0x3070
Bits Name Access Description
[31:0] PCI Express to Avalon-MM
Interrupt Enable
RW When set to 1, enables the interrupt for
the corresponding bit in the
PCI
Express to Avalon MM Interrupt
Status
register to cause the Avalon
Interrupt signal (
cra_Irq_o
) to be
asserted.
Only bits implemented in the
PCI
Express to Avalon MM Interrupt
Status
register are implemented in the
Enable register. Reserved bits cannot be
set to a 1.
6-20 PCI Express to Avalon-MM Interrupt Status and Enable Registers for...
UG-01145_avmm
2015.05.14
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