Features, Features -2 – Altera Arria 10 Avalon-MM User Manual
Page 8
Link Width in Gigabits Per Second (Gbps)
x1
x2
x4
x8
PCI Express Gen2
(5.0 Gbps)
4
8
16
32
PCI Express Gen3
(8.0 Gbps)
7.87
15.75
31.51
63
Refer to AN 456: PCI Express High Performance Reference Design for more information about calculating
bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs, including the Arria 10
Hard IP for PCI Express IP core.
Related Information
•
•
•
Features
New features in the Quartus
®
II 15.0 software release:
• Added Enable Altera Debug Master Endpoint (ADME) parameter to support optional Native PHY
register programming with the Altera System Console.
• Dynamic generation of Qsys design examples using the parameters that you specify.
• Added Root Port support for transmitting messages of length greater than one dword.
The Arria 10 Hard IP for PCI Express with the Avalon-MM interface supports the following features:
• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as
hard IP.
• Support for ×1, ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Root Ports and
Endpoints.
• Dedicated 16 KByte receive buffer.
• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core
bitstreams to be stored separately.
• Support for 32- or 64-bit addressing for the Avalon-MM interface to the Application Layer.
• Qsys example designs demonstrating parameterization, design modules, and connectivity.
• Extended credit allocation settings to better optimize the RX buffer space based on application type.
• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error
reporting (AER) for high reliability applications.
• Easy to use:
• Flexible configuration.
• No license requirement.
• Example designs to get started.
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Features
UG-01145_avmm
2015.05.14
Altera Corporation
Datasheet