Altera Arria 10 Avalon-MM User Manual
Page 28
Parameter
Value
Description
High
Maximum100 MHz
optimize your system. The credit allocation for the selected
setting displays in the message pane.
Refer to the Throughput Optimization chapter for more
information about optimizing performance. The Flow Control
chapter explains how the RX credit allocation and the
Maximum payload RX Buffer credit allocation and the
Maximum payload size that you choose affect the allocation
of flow control credits. You can set the Maximum payload
size parameter on the Device tab.
The Message window dynamically updates the number of
credits for Posted, Non-Posted Headers and Data, and
Completion Headers and Data as you change this selection.
• Minimum—configures the minimum PCIe specification
allowed for non-posted and posted request credits, leaving
most of the RX Buffer space for received completion
header and data. Select this option for variations where
application logic generates many read requests and only
infrequently receives single requests from the PCIe link.
• Low—configures a slightly larger amount of RX Buffer
space for non-posted and posted request credits, but still
dedicates most of the space for received completion header
and data. Select this option for variations where application
logic generates many read requests and infrequently
receives small bursts of requests from the PCIe link. This
option is recommended for typical endpoint applications
where most of the PCIe traffic is generated by a DMA
engine that is located in the endpoint application layer
logic.
• Balanced—configures approximately half the RX Buffer
space to received requests and the other half of the RX
Buffer space to received completions. Select this option for
variations where the received requests and received
completions are roughly equal.
Use 62.5 MHz
application clock
On/Off
This mode is only available only for Gen1 ×1.
Enable byte
parity ports on
Avalon-ST
interface
On/Off
When On, the RX and TX datapaths are parity protected.
Parity is odd.
This parameter is only available for the Avalon-ST Arria 10
Hard IP for PCI Express.
3-2
Arria 10 Avalon-MM System Settings
UG-01145_avmm
2015.05.14
Altera Corporation
Parameter Settings