Altera Arria 10 Avalon-MM - Manual (Page 30)

Interface System Settings
Table 3-2: Interface System Settings
Parameter Value Description
Application Interface
width
64-bit
128-bit
256-bit
Specifies the data width for the Application Layer to
Transaction Layer interface. Refer to Application Layer
Clock Frequency for All Combinations of Link Width,
Data Rate and Application Layer Interface Widths for all
legal combinations of data width, number of lanes,
Application Layer clock frequency, and data rate. The
Avalon-MM with DMA interface does not support the
64-bit interface width.
Avalon-MM address
width
32, 64
Specifies the address width for Avalon-MM RX master
ports that access Avalon-MM slaves in the Avalon
address domain. When you select 32-bit addresses, the
PCI Express Avalon-MM bridge performs address
translation. When you specify 64-bits addresses, no
address translation is performed in either direction. The
destination address specified is forwarded to the
Avalon-MM interface without any changes.
For the Avalon-MM interface with DMA, this value
must be set to 64.
Enable completer-only
Endpoint
On/Off
In this mode, the Hard IP can receive requests, but
cannot initiate upstream requests. However, it can
transmit completion packets on the PCI Express TX
link. This mode removes the Avalon-MM TX slave port
and thereby reduces logic utilization.
Enable completer-only
Endpoint with 4-byte
payload
On/Off
This is a non-pipelined version of Completer Only
mode. At any time, only a single request can be
outstanding. Single dword completer uses fewer
resources than completer only Endpoint. This variant
is targeted for systems that require simple read and
write register accesses from a host CPU. If you select
this option, the width of the data for RXM BAR masters
is always 32 bits, regardless of the Avalon-MM width.
For the Avalon-MM interface with DMA, this value
must be Off .
3-4 Interface System Settings
UG-01145_avmm
2015.05.14
Altera Corporation Parameter Settings
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