Top-level interfaces, Avalon-mm interface, Clocks and reset – Altera Arria 10 Avalon-MM User Manual
Page 121: Interrupts, Pipe, Top-level interfaces -3, Avalon-mm interface -3, Clocks and reset -3, Interrupts -3, Pipe -3
Top-Level Interfaces
Avalon-MM Interface
An Avalon-MM interface connects the Application Layer and the Transaction Layer. The Avalon-MM
interface implement the Avalon-MM protocol described in the Avalon Interface Specifications. Refer to
this specification for information about the Avalon-MM protocol, including timing diagrams.
Related Information
•
64- or 128-Bit Avalon-MM Interface to the Application Layer
on page 5-1
•
Clocks and Reset
The PCI Express Base Specification requires an input reference clock, which is called
refclk
in this design.
The PCI Express Base Specification stipulates that the frequency of this clock be 100 MHz.
The PCI Express Base Specification also requires a system configuration time of 100 ms. To meet this
specification, IP core includes an embedded hard reset controller. This reset controller exits the reset state
after the I/O ring of the device is initialized.
Interrupts
The Hard IP for PCI Express offers the following interrupt mechanisms:
• Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's request-acknowledge
handshaking protocol to implement interrupts. The MSI Capability structure is stored in the Configu‐
ration Space and is programmable using Configuration Space accesses.
• MSI-X—The Transaction Layer generates MSI-X messages which are single dword memory writes. In
contrast to the MSI capability structure, which contains all of the control and status information for
the interrupt vectors, the MSI-X Capability structure points to an MSI-X table structure and MSI-X
PBA structure which are stored in memory.
Related Information
Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled
on page 5-10
PIPE
The PIPE interface implements the Intel-designed PIPE interface specification. You can use this parallel
interface to speed simulation; however, you cannot use the PIPE interface in actual hardware.
• The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation.
• For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants
can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
UG-01145_avmm
2015.05.14
Top-Level Interfaces
10-3
IP Core Architecture
Altera Corporation