Altera Arria 10 Avalon-MM - Manual (Page 3)

Physical Layout of Hard IP In Arria 10 Devices.................................................4-1
Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates..............................................4-4
Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates............................................4-5
Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate...................................... 4-7
64- or 128-Bit Avalon-MM Interface to the Application Layer......................... 5-1
32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals .............................5-3
RX Avalon-MM Master Signals ................................................................................................................5-3
64- or 128-Bit Bursting TX Avalon-MM Slave Signals ..........................................................................5-5
Clock Signals ................................................................................................................................................5-8
Reset...............................................................................................................................................................5-8
Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled .......................................5-10
Hard IP Reconfiguration Interface .........................................................................................................5-11
Physical Layer Interface Signals ..............................................................................................................5-13
Serial Data Signals .........................................................................................................................5-13
PIPE Interface Signals .................................................................................................................. 5-14
Test Signals .................................................................................................................................... 5-19
Registers...............................................................................................................6-1
Correspondence between Configuration Space Registers and the PCIe Specification ..................... 6-1
Type 0 Configuration Space Registers ..................................................................................................... 6-5
Type 1 Configuration Space Registers ..................................................................................................... 6-6
PCI Express Capability Structures.............................................................................................................6-6
Altera-Defined VSEC Registers................................................................................................................. 6-9
CvP Registers..............................................................................................................................................6-10
64- or 128-Bit Avalon-MM Bridge Register Descriptions .................................................................. 6-13
Avalon-MM to PCI Express Interrupt Registers ......................................................................6-15
Programming Model for Avalon-MM Root Port .................................................................................6-26
Sending a Write TLP .................................................................................................................... 6-27
Sending a Read TLP or Receiving a Non-Posted Completion TLP .......................................6-28
PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports ............6-28
Root Port TLP Data Registers ..................................................................................................... 6-29
Uncorrectable Internal Error Mask Register ........................................................................................ 6-31
Uncorrectable Internal Error Status Register ....................................................................................... 6-32
Correctable Internal Error Mask Register .............................................................................................6-33
Correctable Internal Error Status Register ............................................................................................6-34
Arria 10 Reset and Clocks................................................................................... 7-1
Reset Sequence for Hard IP for PCI Express IP Core and Application Layer ....................................7-2
Clocks ........................................................................................................................................................... 7-4
Clock Domains ................................................................................................................................7-4
Clock Summary ...............................................................................................................................7-6
Interrupts for Endpoints .................................................................................... 8-1
TOC-3
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