Compiling the design, Programming a device, Understanding channel placement guidelines – Altera Arria 10 Avalon-MM User Manual
Page 25: Compiling the design -7, Programming a device -7, Understanding channel placement guidelines -7
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
To compile successfully you must add a virtual pin assignment statement for the PIPE interface to
your
.qsf
file. The PIPE interface is useful for debugging, but is not a top-level interface of the IP core.
1. Browse to the synthesis directory that includes the
.qsf
for your project,
synth
2. Open
ep_g2x4_avmm128.qsf
.
3. Add the following assignment statement:
set_instance_assignment -name VIRTUAL_PIN ON -to pcie_a10_hip_0_hip_pipe_*
4. Save the
.qsf
file.
Compiling the Design
1. Before compiling, you need to make a few changes to your top-level Verilog HDL file to create a design
that you can successfully download to a PCB.
a. In the
, open
ep_g2x4_avmm128.v.
b. Comment out the declaration for
pcie_a10_hip_0_hip_ctrl_test_in
.
c. Add a wire
[31:0] pcie_a10_hip_0_hip_ctrl_test_in
declaration to the same the same file.
d. Assign
pcie_a10_hip_0_hip_ctrl_test_in
= 0x000000A8.
e. Connect
pcie_a10_hip_0_hip_ctrl_test_in
to the
test_in
port on the Arria 10 Hard IP for
PCI Express instance.
2. On the Quartus II Processing menu, click Start Compilation.
3. After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note
whether the timing constraints are achieved in the Compilation Report.
If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for
your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design
Space Explorer on the Tools menu.
Programming a Device
After you compile your design, you can program your targeted Altera device and verify your design in
hardware.
For more information about programming Altera FPGAs, refer to Quartus II Programmer.
Related Information
Understanding Channel Placement Guidelines
Arria 10 transceivers are organized in banks of six channels. The transceiver bank boundaries are
important for clocking resources, bonding channels, and fitting. Refer to the Channel Placement for the
Gen1 and Gen2 Data Rates and Channel Placment and fPLL and ATX PLL Usage for the Gen3 Data Rates
for illustrations of channel placement for x1, x2, x4, and x8 variants.
UG-01145_avmm
2015.05.14
Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
2-7
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express
Altera Corporation