Qsys system design for pci express – Altera Arria 10 Avalon-MM User Manual
Page 19
Getting Started with the Avalon‑MM Arria 10
Hard IP for PCI Express
2
2015.05.14
UG-01145_avmm
This Qsys design example provides detailed step-by-step instructions to generate a Qsys system. When
you install the Quartus II software you also install the IP Library. This installation includes design
examples for the Avalon-MM Arria 10 Hard IP for PCI Express in the
altera_pcie_a10_ed/example_design/a10
directory. This walkthrough uses a Gen2 x4 Endpoint,
ep_g2x4_avmm128.qsys.
The design examples contain the following components:
• Avalon-MM Arria 10 Hard IP for PCI Express IP core
• On-Chip memory
• DMA controller
Figure 2-1: Qsys Generated Endpoint
Transaction,
Data Link,
and PHY
Layers
O n-C hip
Memory
DMA
Qsys System Design for PCI Express
PCI Express
Link
PCI
Express
Avalon-MM
Bridge
In
ter
connec
t
Avalon-MM Hard IP for PCI Express
The design example transfers data between an on-chip memory buffer located on the Avalon-MM side
and a PCI Express memory buffer located on the root complex side. The data transfer uses the DMA
component which is programmed by the PCI Express software application running on the Root Complex
processor.
Related Information
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