Altera Arria 10 Avalon-MM - Manual (Page 18)

for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim,
and Synopsys VCS and VCS-MX simulators.
3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II
software you are running do not match, regenerate your PCIe design.
4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐
ment Kits link below for a list of Altera's development boards.
5. Test the hardware. You can use Altera's SignalTap ® II Logic Analyzer or a third-party protocol
analyzer to observe behavior.
6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then
repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test).
The Application Layer logic is typically called APPS.
Related Information
• Parameter Settings on page 3-1
• Getting Started with the Avalon-MM Arria 10 Hard IP for PCI Express on page 2-1
• All Development Kits
1-12 Steps in Creating a Design for PCI Express
UG-01145_avmm
2015.05.14
Altera Corporation Datasheet
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