ADLINK aTCA-N700 - Manual (Page 60)

aTCA-N700 HW Users Guide
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9.5. Managed Objects
The IPMC is responsible to collect and manage the various status of the hardware on
the blade such as sensors, events, and other information.
9.5.1. Temperature Sensor and Real Time Clock
The aTCA-N700 has temperature sensors. The major processors including the
CN6880s, the LMP and the BCM56842 have temperature monitoring sensors for
themselves. The locations of the temperature sensors are all internal to the devices.
There are no external sensors.
The real time clock device is required on the board for management purposes.
9.5.2. Sensor Data Record (SDR)
All the sensors on the board contribute to the Sensor Data Records (SDR). The SDR
include information such as the sensor type, sensor name, and sensor unit. The SDRs
also include the set values such as threshold/hysteresis and the rules for the event
generation. IPMI commands can adjust the values. The IPMC is responsible for saving
the SDR to the EEPROM on the master-only I2C bus. The Shelf Manager can access
these SDR through Sensor Device Commands without knowing the details of the
device characteristics on the board.
9.5.3. System Event Log (SEL)
The SEL is a set of the events generated by the IPMC. The triggering of the events is
by the threshold values monitored by different kinds of sensors. The IPMC is
responsible for the management of the events including detection and saving the SEL
information into the EEPROM. The information includes time stamp, the name of the
sensor, and the cause of the event.
9.5.4. Field Replaceable Unit (FRU) Information
The FRU information contains the service related information that the blade provides,
which includes the board part number, the version, etc. The information is stored in the
EEPROM.
9.6. Storage for IPMC Firmware
The IPMC firmware is composed of the boot code and the operational code, which are
stored into the embedded flash memory of the IPMC, at 512Kbyte. Upon IPMC reset,
the IPMC performs the following operations.
• Device inspection on the master-Only I2C
• IPMC SRAM checking
• IPMB Channel inspection
• IPMC EEPROM information inspection
• FRU information inspection
• Operational Code Checksum inspection
• IPMC active portion of the firmware sanity inspection
After completion of the jobs above, the operational code is executed.
9.7. Blade Reset
The blade level reset signals are controlled by the IPMC. Figure 9-2 illustrates the
device reset signals and their interconnections. The IPMC forwards the command
either initiated by the CPU application or the IPMI application to the CPLD and the
CPLD decodes the command and sends individual reset to the devices accordingly.
Refer to the IPMC and the CPLD pin descriptions for the details.