ADLINK aTCA-N700 - Manual (Page 4)

aTCA-N700 HW Users Guide
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Table of Contents
Revision History.................................................................................................................................. ２
Preface ................................................................................................................................................. ３
List of Figures ..................................................................................................................................... ６
List of Tables ....................................................................................................................................... ７
1. Introduction.................................................................................................................................. ８
2. Summary of Specifications .....................................................................................................１０
3. External Interfaces ...................................................................................................................１２
3.1. Front Panel ............................................................................................................ １２
3.1.1. Console Port ................................................................................................... １２
3.1.2. USB Port ........................................................................................................ １３
3.1.3. Management Ethernet Port .................................................................................. １３
3.1.4. Service Ports ................................................................................................... １３
3.1.5. Reset Switch ................................................................................................... １３
3.1.6. LEDs and Markers............................................................................................. １４
3.2. Zone 2 Backplane Interfaces....................................................................................... １５
3.3. Zone 3 Backplane Interface for Rear Transition Module ...................................................... １５
4. Installation and Operation .......................................................................................................１６
4.1. Hardware Configuration Setting.................................................................................... １７
4.1.1. Headers and Jumpers ........................................................................................ １８
4.1.2. DIP Switch ...................................................................................................... １９
4.1.3. Programmable Devices ...................................................................................... ２１
4.2. Hardware Installation ................................................................................................ ２１
4.2.1. Front Blade ..................................................................................................... ２１
4.2.2. RTM.............................................................................................................. ２２
4.2.3. Console Port Connection .................................................................................... ２３
5. Architecture Overview .............................................................................................................２４
6. Network Processor Subsystem ..............................................................................................２５
6.1. CN6880 Embedded Components ................................................................................. ２６
6.2. DRAM Memory ........................................................................................................ ２７
6.3. Boot/OS Memories on Boot-Bus.................................................................................. ２８
6.4. Data Plane Interface ................................................................................................. ２８
6.5. Mezzanine Board Interface (Optional) ............................................................................ ２９
6.6. Host Interface ......................................................................................................... ３０
6.7. UART Interface ....................................................................................................... ３１
6.8. TWSI (I2C) Interface ................................................................................................. ３１
6.9. Other Interfaces ...................................................................................................... ３１
6.10. GPIO .................................................................................................................... ３２
6.11. Clock ................................................................................................................... ３２
7. Data Plane Interconnection Subsystem.................................................................................３４
7.1. Switch Features: BCM56842 ....................................................................................... ３４
7.2. SerDes Interface...................................................................................................... ３４
7.3. PCI-e Interface ....................................................................................................... ３６
7.4. Reset and Interrupts ................................................................................................. ３６
7.5. Clock ................................................................................................................... ３７
7.6. Other Interfaces ...................................................................................................... ３７
7.6.1. MDC/MDIO: MIIM .............................................................................................. ３７
7.6.2. BSC (I2C) Interface ........................................................................................... ３７
7.6.3. LED Control .................................................................................................... ３７
7.6.4. JTAG............................................................................................................. ４０
8. Control Plane Subsystem........................................................................................................４１
8.1. Local Management Processor, P2041 ........................................................................... ４２
8.1.1. Features ........................................................................................................ ４２
8.1.2. DDR3 SDRAM Interface ...................................................................................... ４３
8.1.3. PCI Express Interface......................................................................................... ４４
8.1.4. I2C (TWSI) Interface .......................................................................................... ４４
8.1.5. UART Interface ................................................................................................ ４６
8.1.6. Interrupts........................................................................................................ ４７
8.1.7. SPI Interface ................................................................................................... ４８