ADLINK aTCA-N700 - Manual (Page 6)

aTCA-N700 HW Users Guide
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List of Figures
Figure 3-1 aTCA-N700 Front Panel .......................................................................................１２
Figure 4-1 aTCA-N700 ...........................................................................................................１６
Figure 4-2 Configurable Component Locations......................................................................１７
Figure 4-3 CPLD JTAG Header ...........................................................................................１８
Figure 4-4 COP Header .......................................................................................................１８
Figure 4-5 Standalone Mode Selector Header.......................................................................１８
Figure 4-6 In/Ejector handle (bottom side) .............................................................................２２
Figure 4-7 Plugging the Board ...............................................................................................２２
Figure 5-1 aTCA-N700 Architecture with optional RTMs .......................................................２４
Figure 6-1 Network Processor Subsystem.............................................................................２６
Figure 6-2 CN68XX Internal Blocks .......................................................................................２７
Figure 6-3 CN6880 DRAM Memory .......................................................................................２７
Figure 6-4 Boot Memories ......................................................................................................２８
Figure 6-5 Data Path Interface ...............................................................................................２９
Figure 6-6 Mezzanine Board Interface ...................................................................................２９
Figure 6-7 Mezzanine Board Connector ................................................................................２９
Figure 6-8 Host Interface – PCIe............................................................................................３０
Figure 6-9 Host Interface - Ethernet.......................................................................................３０
Figure 6-10 Console Port Connection ....................................................................................３１
Figure 6-11 TWSI (I2C) Connection.......................................................................................３１
Figure 6-12 External clock to CN6880 requirements .............................................................３３
Figure 7-1 Switch Port Connections .......................................................................................３５
Figure 7-2 Switch Reset Requirements..................................................................................３６
Figure 7-3 Switch LED_DATA0 Format .................................................................................３７
Figure 8-1 Control Plane Subsystem .....................................................................................４１
Figure 8-2 P2041 Internal Blocks (from datasheet) ...............................................................４２
Figure 8-3 P2041 DDR3 Interface..........................................................................................４３
Figure 8-4 Host Interface – PCI-e ..........................................................................................４４
Figure 8-5 P2041 I2C Interface ..............................................................................................４５
Figure 8-6 P2041 UART Interface..........................................................................................４６
Figure 8-7 P2041 SPI Interface ..............................................................................................４８
Figure 8-8 P2041 Local Bus (EBI) Interface...........................................................................４９
Figure 8-9 Ethernet Control Plane Interconnections ..............................................................５０
Figure 9-1 IPMC Block ...........................................................................................................５３
Figure 9-2 Blade Reset Signals..............................................................................................６１
Figure 9-3 Cold Reset Procedure...........................................................................................６２
Figure 9-4 Deactivate Procedure ...........................................................................................６２
Figure 9-5 Activate Procedure................................................................................................６３
Figure 9-6 RTM Deactivate Procedure...................................................................................６３
Figure 9-7 RTM Activate Procedure.......................................................................................６４
Figure 9-8 Shutdown Procedure ............................................................................................６５
Figure 9-9 RTM Shutdown Procedure....................................................................................６５
Figure 9-10 Hot Swap Procedure ...........................................................................................６６
Figure 9-11 RTM Hot Swap Procedure ..................................................................................６７
Figure 10-1 Power Distribution ...............................................................................................７１
Figure 10-2 Power Sequencing ..............................................................................................７２
Figure 11-1 IPMC and CPLD Clocks......................................................................................７３
Figure 11-2 Clocks for NPUs, LMP, and Switch Fabric .........................................................７４
Figure 12-1 Faceplate and component placement.................................................................７５
Figure 12-2 PCB layer stack-up (preliminary) ........................................................................７６