ADLINK aTCA-N700 - Manual (Page 25)

aTCA-N700 HW Users Guide
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6. Network Processor Subsystem
The major component of the network processor subsystem is the OCTEON II, CN6880
network processor from Cavium. OCTEON CN68XX family devices provide an architecture
that guarantees software backward compatibility for CN5XXX family. The CN68XX family
devices use the same cnMIPS II CPU core and same on-chip architecture. The features of
the CN68XX are summarized as the following.
•
Highly-integrated networking security/application processor
•
MIPS64® integer instruction set, highly programmable
•
High-performance architecture with up to 32 cnMIPS™ II processor cores
•
Dual control- and data-plane support
•
Standalone (i.e. self-bootable) or device support
•
Core frequency up to 1.5 GHz, producing up to 96.0 GOPS in a single chip
•
Line-rate performance of 40 Gbps with small packets
• Excellent performance/watt
•
Hardware cryptographic (MD5, SHA-1, SHA-256, SHA-512, DES/3DES, AES,
KASUMI, SNOW 3G, SMS4, modular exponentiation, and Galois field multiplication)
and CRC acceleration
•
Hardware packet processing acceleration
•
Hardware work queuing, scheduling, ordering, and synchronization
•
Hardware TCP acceleration, including checksum and timer
•
High-bandwidth on-chip memory system including a 4MB 16-way set-associative L2
cache
•
Fully coherent memory system
•
Quad 72-bit DDR3 DRAM interfaces, up to 1333 MHz data rate
•
Support for DDR3L 1.35-mode operation
•
Hardware regular expression acceleration engine (3rd generation)
•
One USB 2.0 MAC/PHY
•
One RGMII or MII interface
•
Up to three packet interfaces with either SGMII (up to ×4) or XAUI (×4)07/18/2011
•
Up to two RXAUI interfaces
•
Two optional PCI Express® (PCIe®) 2.0 interfaces with Ч1/Ч2/Ч4/Ч8 lanes
•
One optional Interlaken (ILK) controller with Ч1/Ч2/Ч4 dedicated lanes or ×8 using
four additional shared lanes (shared with one of the SGMII/XAUI interfaces)
•
Secure on-chip key memory
•
Cryptographic random-number generator
•
Option to boot using NAND flash device
• Hardware
compression/decompression acceleration
•
Hardware RAID acceleration
•
Hardware de-duplication acceleration
Figure 6-1 illustrates the Network Processor Subsystem. The blade has two identical sets of
CN6880 circuitry. There is an optional mezzanine board which may have TCAM(s). The
mezzanine board is connected to both CN6880s in 4 lanes of Interlaken-LA interface. Each
set of NPUs has its own NOR boot flash memory and NAND OS flash memory in a redundant
configuration. Four VLP DIMMs per NPU are populated on the board to host up to 32GB
(8GB per DIMM module, but expandable further to 120GB with higher density memory
modules when available). 40Gbps capacity of the data path per NPU is connected to the
fabric switch with two RXAUIs and two XAUIs interfaces. The control path is connected to the
base switch in RGMII interface and in PCI express to the P2041 LMP.