GW Instek GDS-2000A series Option User Manual - Manual (Page 14)

GDS-2000A Series Options Manual
14
Trigger - Logic
Clock Edge When Threshold Define Inputs
D0~D15
Select
Clock
High ( H )
Low ( L )
Don’t Care
( X )
5%
5%
Goes Goes
True False
Is True <
XXns
Is True =
XXns
Is True ≠
XXns
Is True >
XXns
D0~D3
D4~D7
D8~D11
D12~D15
Select
XX~XXV
Threshold
User
TTL
5.0V CMOS
3.3V CMOS
2.5V CMOS
ECL
PECL
0V
Choose Preset
Type
Logic
Mode Holdof
Auto
Normal
10.0ns ~ 10.0s
Set to
Minimum
*The source bus is determined from the bus menu.
Bus
Bus
UART
I 2 C
SPI
Parallel
B
BUS
B
Goes to the UART bus menu
Goes to the I 2 C bus menu
Goes to the SPI bus menu
Goes to the Parallel bus menu