Rainbow Electronics DS2180A User Manual

Page 26

DS2180A

041995 26/36

TRANSMIT SIDE OVERVIEW

The transmit side of the DS2180A is made up of six ma-
jor functional blocks: timing and clock generation, data
selector, bipolar coder, yellow alarm, F-bit data and
CRC. The timing and clock generation circuit develops
all onboard and output clocks to the system from inputs
TCLK, TFSYNC, and TMSYNC. The yellow alarm cir-
cuitry generates mode–dependent yellow alarms. The
CRC block generates checksum results utilized in 193E
framing. F-bit data provides mode–dependent framing
patterns and allows insertion of link or S-bit data exter-
nally. All of these blocks feed into the data selector
where, under control of the CCR, TCR, TIRs and TTRs,
the contents of the outgoing data stream are estab-
lished by bit selection and insertion. The bipolar coder
formats the output of the data selector to make it com-
patible with bipolar transmission techniques and inserts
zero suppression codes. The bipolar coder also sup-
ports the onboard loopback feature. Input-to-output
delay of the transmitter is 10 TCLK cycles.

RECEIVE SIDE OVERVIEW
Synchronizer

The heart of the receiver is the synchronizer monitor.
This circuit serves two purposes: 1) monitoring the in-
coming data stream for loss of frame or multiframe
alignment, and 2) searching for new frame alignment
pattern when sync loss is detected. When sync loss is
detected, the synchronizer begins an off-line search for
the new alignment; all output timing signals remain at
the old alignment with the exception of RSIGFR which is
forced low during resync. When one and only one candi-
date is qualified, the output timing will move to the new
alignment at the beginning of the next multiframe. One
frame later, RLOS will transition low, indicating valid
sync and the resumption of the normal sync monitoring
mode. Several bits in the RCR allow tailoring of the re-
sync algorithm by the user. These bits are described be-
low.

Sync Time (RCR.2)

Bit RCR.2 determines the number of consecutive fram-
ing pattern bits to be qualified before SYNC is declared.
If RCR.2=1, the algorithm will validate 24 bits; if
RCR.2=0, 10 bits are validated. 24-bit testing results in
superior false framing protection, while 10-bit testing
minimizes reframe time (although in either case, the
synchronizer will only establish resync when one and
only one candidate is found).

Resync (RCR.0)

A zero-to-one transition of RCR.0 causes the synchro-
nizer to search for the framing pattern sequence im-
mediately, regardless of the internal sync status. In or-
der to initiate another resync command, this bit must be
cleared and then set again.

Sync Enable (RCR.1)

When RCR.1 is cleared, the receiver will initiate auto-
matic resync if any of the following events occur: 1) an
OOF event (“out-of-frame”), or 2) carrier loss (32 con-
secutive 0’s appear at RPOS and RNEG). An OOF
event occurs any time that 2 of 4 F

or FPS bits are in

error. When RCR.1 is set, the automatic resync circuitry
is disabled; in this case, resync can only be initiated by
setting RCR.0 to 1 or externally via a low-high transition
on RST. Note that using RST to initiate resync resets the
receive output timing while RST is low; use of RCR.1
does not affect output timing until the new alignment is
located.

Sync Criteria (RCR.3)

193E
Bit RCR.3 determines which sync algorithm is utilized
when resync is in progress (RLOS=1). In 193E framing,
when RCR.3=0, the synchronizer will lock only to the
FPS pattern and will move to the new frame and multi-
frame alignment after the move to the new alignment.
When RCR.3=1, the new alignment is further tested by a
CRC code match. RLOS will transition low after a CRC
match occurs. If no CRC match occurs in three attempts
(three multiframes), the algorithm will reset and a new
search for the framing pattern begins. It takes 9 ms for
the synchronizer to check the first CRC code after the
new alignment has been loaded. Each additional CRC
test takes 3 ms. Regardless of the state of RCR.3, if
more than one candidate exists after about 24 ms, the
synchronizer will begin eliminating emulators by testing
their CRC codes online in order to find the true framing
candidate.

193S
In 193S framing, when RCR.3=1, the synchronizer will
cross check the F

pattern with the F

pattern to help

eliminate false framing candidates such as digital milli-
watts. The F

patterns are compared to the

repeating pattern ...00111000111000...(00111X0 if
CCR.3–YELMD–is equal to a 1). In this mode, F

and

patterns must be correctly identified by the synchro-