Rainbow Electronics W79E8213R - Manual (Page 56)

Preliminary W79E8213/W79E8213R Data Sheet
Publication Release Date: July 11, 2008
- 56 - Revision A2
12. INTERRUPTS
The W79E8213 series have four priority level interrupts structure with 10 interrupt sources. Each of
the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
12.1 Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, programmable
through bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the
external interrupts are sampled every machine cycle, they have to be held high or low for at least one
complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the
level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is
serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced.
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the time-
out count is reached, the Watchdog Timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt will occur.
PWM interrupt is generated when its’ 10-bit down counter underflows. PWMF flag is set and PWM
interrupt is generated if enabled. PWMF is set by hardware and can only be cleared by software.
Alternatively, PWM function can also generate interrupt by BKF flag, after external brake pin has brake
occurred. This bit will be cleared by software.
The ADC can generate interrupt after finished ADC converter. There is one interrupt source, which is
obtained by the ADCI bit in the ADCCON SFR. This bit is not automatically cleared by the hardware,
and the user will have to clear this bit using software.
Edge detect interrupt is generated when any of the keypad connected to P1.0-P1.2 pins is pressed.
Each edge detect interrupt can be individually enabled/disabled. User will have to software clear the
flag bit. The ED pins have edge type and filter type control, configurable through EDIC SFR.
Brownout detect can cause brownout flag, BOF, to be asserted if power voltage drop below brownout
voltage level. Interrupt will occur if BOI (AUXR1.5), EBO (IE.5) and global interrupt enable are set.
All the bits that generate interrupts can be set or reset by software, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all interrupts.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being execute.
3. The current instruction does not involve a write to IE, EIE, IP0, IP0H, IP1 or IPH1 registers and is
not a RETI.