Rainbow Electronics W79E8213R - Manual (Page 55)

Preliminary W79E8213/W79E8213R Data Sheet
Publication Release Date: July 11, 2008
- 55 - Revision A2
11.1.3 Watchdog Timer Reset
The Watchdog Timer is a free-running timer with programmable time-out intervals. The program must
clear the Watchdog Timer before the time-out interval is reached to restart the count. If the time-out
interval is reached, an interrupt flag is set. 512 clocks later, if the Watchdog Reset is enabled and the
Watchdog Timer has not been cleared, the Watchdog Timer generates a reset. The reset condition is
maintained by the hardware for two machine cycles, and the WTRF bit in WDCON is set. Afterwards,
the device begins program execution at 0000h.
11.2 Reset State
When the device is reset, most registers return to their initial state. The Watchdog Timer is disabled if
the reset source was a power-on reset. The port registers are set to FFh, which puts most of the port
pins in a high state. The Program Counter is set to 0000h, and the stack pointer is reset to 07h. After
this, the device remains in the reset state as long as the reset conditions are satisfied.
Reset does not affect the on-chip RAM, however, so RAM is preserved as long as VDD remains
above approximately 2V, the minimum operating voltage for the RAM. If VDD falls below 2V, the RAM
contents are also lost. In either case, the stack pointer is always reset, so the stack contents are lost.
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset. The
WDCON SFR is set to a 0x00 0000B on the reset. WTRF (WDCON.2) is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF (WDCON.2) is not altered by external reset. EWRST
(WDCON.1) is cleared by any reset. Software or any reset will clear WDIF (WDCON.3) bit.
Some of the bits in the WDCON SFR (WDRUN, WDCLR, EWRST, WDIF, WD0 and WD1) have
unrestricted read access which required Timed Access procedure to write. The remaining bits have
unrestricted write accesses. Please refer TA register description.
For all SFR reset state values, please refer to Table 8-2: Special Function Registers.