Rainbow Electronics MAXQ3108 - Manual (Page 57)

MAXQ3108
Low-Power, Dual-Core Microcontroller
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The other party, the slave, recognizes its address and
responds by accepting data or delivering data. A data
transfer sequence can be grouped into the following
stages:
• START: The master generates the START condition
(S) by pulling SDA low (high-to-low transition) while
holding SCL high.
• Address: The master transmits the address of the
slave device, together with the direction of data
transfer (R/W).
• Address Acknowledge: The slave with the matching
address responds to the master by holding SDA low
during the 9th clock SCL high (A).
• Data: The transmitter sends data to the receiver. The
number of bytes of data is unlimited. However, each
data byte must be followed by a data-acknowledge
bit (A).
• Data Acknowledge: The receiver acknowledges to
the transmitter by sending the acknowledge bit (A). If
the master is the receiver and the data just received
is the last byte expected, the master leaves SDA
high to signal to the slave transmitter that the last
byte of expected data is transmitted. The slave trans-
mitter then releases SDA after the 9th clock so that
the master can generate a STOP or START condition.
• STOP: The master concludes the transfer by send-
ing the STOP condition (P) by causing a low-to-high
transition on SDA while SCL is high. The I
2 C bus is
now idle.
The MAXQ3108 I 2 C peripheral uses seven registers to
manage I 2 C bus communication:
• I2CBUF: The buffer register through which all out-
bound data is written, and through which all inbound
data is received.
• I2CCK: The I 2 C clock register defines the high and
low periods for the SCL signal.
• I2CCN: The control register manages the I 2 C periph-
eral during configuration and operation.
• I2CST: The status register contains bits that reflect
the condition of the I 2 C peripheral. It is consulted fre-
quently during I 2 C operation.
• I2CIE: The interrupt enable register is used to man-
age interrupt sources within the I 2 C peripheral.
• I2CTO: The timeout register defines how long a slave
can extend the I 2 C clock before the peripheral
declares a timeout.
• I2CSLA: Establishes the slave address for the I 2 C
peripheral.
I 2 C Use Scenario: MAXQ3108 Master Sends 2 Bytes
to Slave
1) Set the I2CEN and I2CMST bits in the I2CCN regis-
ter. This enables the I 2 C peripheral and establishes
the MAXQ3108 as master.
2) Set the I2CSTART bit in the I2CCN register. This
causes the MAXQ3108 to send the START
sequence. When the START condition has been
sent (and both SDA and SCL are low), the
I2CSTART bit is cleared. Note that the I2CSRI bit is
set in the I2CST register as well. That is because
the I
2 C peripheral sees its own START condition.
3) Load the command byte into I2CBUF. The com-
mand byte consists of the slave address and the
R/W bit. For this example, assume we wish to write
to slave address 0x30. The byte to be loaded in this
case is 0x60: the address shifted up by one posi-
tion and bit 0 (the R/W bit) set to 0.
4) Monitor the I2CTXI flag in the I2CST register. When
set, the I 2 C peripheral has finished sending the
command byte and has received an ACK or a NAK
from the remote device. Check the I2CNACKI flag in
the I2CST register to determine if an ACK or a NAK
was received. If set, the command was not acknowl-
edged. Clear these bits after they are tested.
5) Load the first data byte into I2CBUF.
6) Monitor the I2CTXI flag in the I2CST register. When
set, the I 2 C peripheral has finished sending the
data byte. Check the I2CNACKI flag to ensure that
the slave has received the byte. Clear both these
bits.
7) Load the second data byte into I2CBUF.
8) Monitor the I2CTXI flag in the I2CST register. When
set, the I 2 C peripheral has finished sending the
data byte. Check the I2CNACKI flag to ensure that
the slave has received the byte. Clear both these
bits.
9) Set the I2CSTOP bit in the I2CCN register. This
causes the MAXQ3108 to send the STOP
sequence. When this bit returns to 0, the STOP
sequence has been sent and the I
2 C bus is idle.
I 2 C Use Scenario: MAXQ3108 Master Receives 2
Bytes from Slave
1) Set the I2CEN and I2CMST bits in the I2CCN regis-
ter. This enables the I 2 C peripheral and establishes
the MAXQ3108 as master.
2) Set the I2CSTART bit in the I2CCN register. This
causes the MAXQ3108 to send the START
sequence. When the START condition has been