Rainbow Electronics MAXQ3108 - Manual (Page 36)

MAXQ3108
Low-Power, Dual-Core Microcontroller
36 ______________________________________________________________________________________
Special Function Register Bit Descriptions (continued)
SMD0.7: EPWM
Enable TXD PWM Output Function. Setting this bit to a 1 enables the output of the logical function
selected by the OFS bit to be output on the TXD0 pin for the asynchronous UART transmit modes
(i.e., modes 1, 2, and 3). Note that the PWM function is not possible for UART mode 0 and this bit
has no effect during UART mode 0 operation. When this bit is cleared to 0, the OFS bit is
meaningless and the normal TXD0 pin controls and behavior apply.
PR0 (09h, 02h) Phase Register 0
Initialization: The phase register is cleared to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write.
PR0.[15:0]:
Phase Register 15:0. This register is used to load and read the 16-bit value in the phase register
that determines the baud rate for the serial port 0.
PD2 (0Ah, 02h) Port 2 Direction Register
Initialization: This register is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
PD2.[6:0]:
Port 2 Direction Register Bits 6:0. PD2 is used to determine the direction of the port 2 function. The
port pins are independently controlled by their direction bit. When a bit is set to 1, its corresponding
pin is used as an output; data in the PO register is driven on the pin. When a bit is cleared to 0, its
corresponding pin is used as an input, and allows an external signal to drive the pin. Note that each
port pin has a weak pullup circuit when functioning as an input and the p-channel pullup transistor is
controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is on; if the PO bit is
cleared to 0, the weak pullup is off and forces the port pin into three-state.
PD2.7: Reserved Reserved. Reads return 0.
T2CNB (0Bh, 02h) Timer 2 Control Register B
Initialization: This register is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
T2CNB.0: TC2L
Timer 2 Low Compare Flag. This flag is meaningful only for the dual 8-bit mode of operation (T2MD
= 1) and becomes set only when a compare match occurs between T2CL and T2L. Timer 2 low
does not have an associated capture function.
T2CNB.1: TCC2
Timer 2 Capture/Compare Flag. This flag is set on any compare match between the Timer 2 value
and compare register (T2V = T2C or T2H = T2CH, respectively, for 16-bit and 8-bit compare modes)
or when a capture event is initiated by an external edge.
T2CNB.2: TF2L
Timer 2 Low Overflow Flag. This flag is meaningful only when in the dual 8-bit mode of operation
(T2MD = 1) and becomes set whenever there is an overflow of the T2L 8-bit timer.
T2CNB.3: TF2
Timer 2 Overflow Flag. This flag becomes set anytime there is an overflow of the full 16-bit T2
timer/counter (when T2MD = 0) or an overflow of the 8-bit T2H timer/counter when the dual 8-bit
mode of operation is selected (T2MD = 1).
T2CNB.4: Reserved Reserved. Reads return 0.
T2CNB.5: T2POL1
Timer 2 Polarity Select 1. When the T2B output is enabled (T2OE1 = 1), this bit selects the starting
logic level for the alternate pin output. The output that is driven on the T2PB pin can be derived
from the 16-bit timer 2 or the 8-bit timer (T2L) depending upon whether operating in the 16-bit mode
or the dual 8-bit mode. The T2POL1 bit can be modified any time, but takes effect on the external
pin when T2OE1 is changed from 0 to 1.