Rainbow Electronics MAXQ3108 - Manual (Page 37)

MAXQ3108
Low-Power, Dual-Core Microcontroller
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Special Function Register Bit Descriptions (continued)
T2CNB.6: T2OE1
Timer 2 Output Enable 1. See the table given under T2CNA. 5 bit description. The T2OE1 bit is not
implemented for single pin versions of timer 2.
T2CNB.7: ET2L
Enable Timer 2 Low Interrupts. This bit serves as the local enable for timer 2 low interrupt sources
that fall under the TF2L and TC2L interrupt flags.
T2V (0Ch, 02h) Timer 2 Value Register
Initialization: This register is cleared to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write.
T2V.[15:0]:
Timer 2 Value Register Bits 15:0. The T2V register is a 16-bit register that holds the current timer 2
value. When operating in 16-bit mode (T2MD = 0), the full 16 bits are read/write accessible. If the
dual 8-bit mode of operation is selected, the upper byte of T2V is inaccessible. T2V reads while in
the dual 8-bit mode return 00h as the high byte and writes to the upper byte of T2V are blocked. A
separate T2H register is provided to facilitate high-byte access.
T2R (0Dh, 02h) Timer 2 Reload Register
Initialization: This register is cleared to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write.
T2R.[15:0]:
Timer 2 Reload Register Bits 15:0. This 6-bit register holds the reload value for timer 2. When
operating in 16-bit mode (T2MD = 0), the full 16 bits are read/write accessible. If the dual 8-bit
mode of operation is selected, the upper byte of T2R is inaccessible. T2R reads while in the dual
8-bit mode return 00h as the high byte and writes to the upper byte of T2R are blocked. A separate
T2RH register is provided to facilitate high-byte access.
T2C (0Eh, 02h) Timer 2 Capture/Compare Register
Initialization: This register is cleared to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write.
T2C.[15:0]:
Timer 2 Capture/Compare Register Bits 15:0. This 16-bit register that holds the compare value
when operating in compare mode and gets the capture value when operating in capture mode.
When operating in 16-bit mode (T2MD = 0), the full 16 bits are read/write accessible. If the dual 8-
bit mode of operation is selected, the upper byte of T2C is inaccessible. T2C reads while in the
dual 8-bit mode return 00h as the high byte and writes to the upper byte of T2C are blocked. A
separate T2CH register is provided to facilitate high-byte access.
T2CFG (0Fh, 02h) Timer 2 Configuration Register
Initialization: This register is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
T2CFG.0: C/T2
Timer 2 Counter/Timer Select. This bit enables/disables the edge counter mode of operation for
the 16-bit counter (T2H:T2L) or the 8-bit counter (T2H) when the dual 8-bit mode of operation is
enabled (T2MD = 1). The edge for counting (rising/falling/both) is defined by the CCF[1:0] bits.
0: timer mode
1: counter mode