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Maxq3108 low-power, dual-core microcontroller – Rainbow Electronics MAXQ3108 User Manual

Page 43

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MAXQ3108

Low-Power, Dual-Core Microcontroller

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43

Special Function Register Bit Descriptions (continued)

I2CST.1: I2CTXI

I

2

C Transmit Complete Interrupt Flag. This bit indicates that an address or a data byte has been

successfully shifted out and the I

2

C controller has received an acknowledgment from the receiver

(NACK or ACK). This bit must be cleared by software once set. Setting this bit to 1 by software
causes an interrupt if enabled.

I2CST.2: I2CRXI

I

2

C Receive Ready Interrupt Flag. This bit indicates that a data byte has been received in the I

2

C

buffer. This bit must be cleared by software once set. Setting this bit to 1 by hardware causes an
interrupt if enabled. This bit is set by hardware only.

I2CST.3: I2CSTRI

I

2

C Clock Stretch Interrupt Flag. This bit indicates that the I

2

C controller is operating with clock

stretching enabled and is holding the SCL clock signal low. The I

2

C controller releases SCL after

this bit has been cleared to 0. Setting this bit to 1 by hardware causes an interrupt if enabled. This
bit must be cleared to 0 by software once set. This bit is set by hardware only.

I2CST.4: I2CTOI

I

2

C Timeout Interrupt Flag. This bit is set to 1 if either the I

2

C controller cannot generate a START

condition or the I

2

C SCL low time has expired the timeout value specified in I2CTO register. This

happens when the I

2

C controller is operating in master mode and some other device on the bus is

using the bus or holding SCL low for an extended period of time. This bit must be cleared to 0 by
software once set. Setting this bit to 1 by software causes an interrupt if enabled.

I2CST.5: I2CAMI

I

2

C Slave Address Match Interrupt Flag. This bit is set to 1 when the I

2

C controller receives an

address that matches the contents in its slave address register (I2CSLA) during the address stage.
This bit must be cleared to 0 by software once set. Setting this bit to 1 by software causes an
interrupt if enabled.

I2CST.6: I2CALI

I

2

C Arbitration Loss Flag. This bit is set to 1 when the I

2

C is configured as a master and loses in

the arbitration. When the master loses arbitration, the I2CMST bit is cleared to 0. Setting this bit to 1
by hardware causes an interrupt if enabled. This bit must be cleared to 0 by software once set.
This bit is set by hardware only.

I2CST.7: I2CNACKI

I

2

C NACK Interrupt Flag. This bit is set to 1 if the I

2

C transmitter receives a NACK from the

receiver. Setting this bit to 1 by hardware causes an interrupt if enabled. This bit must be cleared to
0 by software once set. This bit is set by hardware only.

I2CST.8: I2CGCI

I

2

C General Call Interrupt Flag. This bit is set to 1 when the general call is enabled (I2CGCEN = 1)

and the general call address is received. This bit must be cleared to 0 by software once set.
Setting this bit to 1 by software causes an interrupt if enabled.

I2CST.9: I2CROI

I

2

C Receiver Overrun Flag. This bit indicates a receive overrun when set to 1. This bit is set to 1 if

the receiver has already received two bytes since the last CPU read. This bit is cleared to 0 by
software reading the I2CBUF. Setting this bit to 1 by software causes an interrupt if enabled. Writing
0 to this bit does not clear the interrupt.

I2CST.10: I2CSCL

I

2

C SCL Status. This bit reflects the logic state of the SCL signal. This bit is set to 1 when SCL is

at a logic-high (1), and cleared to 0 when SCL is at a logic-low (0). This bit is controlled by
hardware and is read-only.

I2CST.11: I2CSPI

I

2

C STOP Interrupt Flag. This bit is set to 1 when a STOP condition (P) is detected. This bit must be

cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.

I2CST.[13:12]: Reserved

Reserved. Reads return 0.

I2CST.14: I2CBUSY

I

2

C Busy. This bit is used to indicate the current status of the I

2

C module. The I2CBUSY is set to 1

when the I

2

C controller is actively participating in a transaction or when it does not have control of

the bus. This bit is controlled by hardware and is read only.

I2CST.15: I2CBUS

I

2

C Bus Busy. This bit is set to 1 when a START/REPEATED START condition is detected and

cleared to 0 when the STOP condition is detected. This bit is reset to 0 on all forms of reset and
when I2CEN = 0. This bit is controlled by hardware and is read-only.

See also other documents in the category Rainbow Electronics Sensors: