Rainbow Electronics MAXQ3108 - Manual (Page 45)

MAXQ3108
Low-Power, Dual-Core Microcontroller
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Special Function Register Bit Descriptions (continued)
TB0C (05h, 04h) Timer B 0 Compare
Initialization: This register is cleared to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write.
TB0C.[15:0]:
Timer B Compare Bits 15:0. This register is used for comparison versus the TBV value when timer
B is operated in compare mode.
SCON1 (06h, 04h) Serial Port 1 Control Register
Initialization: The serial port control is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
SCON1.0: RI
Receive Interrupt Flag. This bit indicates that a data byte has been received in the serial-port
buffer. The bit is set at the end of the 8th bit for mode 0, after the last sample of the incoming stop
bit for mode 1 subject to the value of the SM2 bit, or after the last sample of RB8 for modes 2 and
3. This bit must be cleared by software once set.
SCON1.1: TI
Transmit Interrupt Flag. This bit indicates that the data in the serial-port data buffer has been
completely shifted out. It is set at the end of the last data bit for all modes of operation and must
be cleared by software once set.
SCON1.2: RB8
9th Received Bit State. This bit identifies the state of the 9th bit of received data in serial-port
modes 2 and 3. When SM2 is 0, it is the state of the stop bit in mode 1. This bit has no meaning in
mode 0.
SCON1.3: TB8
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial-port
modes 2 and 3.
SCON1.4: REN
Receive Enable
REN_0 = 0: Serial port 0 receiver disabled.
REN_0 = 1: Serial port 0 receiver enabled for modes 1, 2, and 3. Initiate synchronous reception
for mode 0.
SCON1.5: SM2
Serial Port 1 Mode Bit 2. Setting this bit in mode 1 ignores reception if an invalid stop bit is
detected. Setting this bit in mode 2 or 3 enables multiprocessor communications, and prevents the
RI bit from being set and the interrupt from being asserted if the 9th bit received is 0. This bit also
used to support mode 0 for clock selection.
SM2 = 0: clock is divided by 12.
SM2 = 1: clock is divided by 4.
SCON1.6: SM1 Serial Port 1 Mode Bit 1
SCON1.7: SM0/FE
Serial Port 1 Mode Bit 0/Framing Error Flag. When FEDE is 0, this bit is SM0. When FEDE is set to
1, this bit is the FE flag that is set upon detection of an invalid stop bit. It must be cleared by
software. Modification of this bit when FEDE is set has no effect on the serial mode. See the table
in the SCON0.7 bit description for guidelines.
SBUF1 (07h, 04h) Serial Data Buffer 1
Initialization: This buffer is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
SBUF1.[7:0]:
Serial Data Buffer 1 Bit 7:0. Data for serial port 0 is read from or written to this location. The
serial transmit and receive buffers are separate but both are addressed at this location.