Rainbow Electronics MAXQ3108 - Manual (Page 19)

MAXQ3108
Low-Power, Dual-Core Microcontroller
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Special Function Register Bit Descriptions (continued)
MREQ1 (0Fh, 00h) Master Request Register 1
Initialization: This register is reset to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write access only to the UserCore.
Unrestricted read access only to the DSPCore.
MREQ1.[15:0]:
Master Request Register 1 Bits 15:0. These bits are used to supply follow-on address and data
information for commands issued by the master. To notify the slave that data is ready to be read,
the REQCDV bit should be set to 1. The master should poll the REQCDV bit to know when the slave
has read MREQ1 and when it is safe to write further data to MREQ1.
MREQ2 (10h, 00h) Master Request Register 2
Initialization: This register is reset to 0000h on all forms of reset.
Read/Write Access: Unrestricted read/write access only to the UserCore.
Unrestricted read access only to the DSPCore.
MREQ2.[15:0]:
Master Request Register 2 Bits 15:0. These bits are used to supply follow-on address and data
information for commands issued by the master. To notify the slave that data is ready to be read,
the REQCDV bit should be set to 1. The master should poll the REQCDV bit to know when the slave
has read MREQ2 and when it is safe to write further data to MREQ2.
ADCN (11h, 00h) Analog-to-Digital Converter Control Register
Initialization: This register is cleared to 0000h on all forms of reset.
Read/Write Access: UserCore: Unrestricted read/write access except bits 0:5 are read only and 6:7 have hardware
restricted write access.
DSPCore: Read-only.
ADCN.0: ABF0
ADC0 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from
ADC0. An interrupt request is generated to a CPU if IF01E = 1 and interrupts are not otherwise
masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore
or the DSPCore) of the AD0 output register. The ABF0 and ABF1 flags are set in the same clock
cycle.
ADCN.1: ABF1
ADC1 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from
ADC1. An interrupt request is generated to a CPU if IF01E = 1 and interrupts are not otherwise
masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore
or the DSPCore) of the AD1 output register. The ABF0 and ABF1 flags are set in the same clock
cycle.
ADCN:2: ABF2
ADC2 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from
ADC2. An interrupt request is generated to a CPU if IF23E = 1 and interrupts are not otherwise
masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore
or the DSPCore) of the AD2 output register. The ABF2 and ABF3 flags are set in the same clock
cycle.
ADCN.3: ABF3
ADC3 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from
ADC3. An interrupt request is generated to a CPU if IF23E = 1 and interrupts are not otherwise
masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore
or the DSPCore) of the AD3 output register. The ABF2 and ABF3 flags are set in the same clock
cycle.
ADCN.4: ABF4
ADC4 Buffer Full Flag. This bit is set by hardware to indicate that a sample is available from
ADC4. An interrupt request is generated to a CPU if IF45E = 1 and interrupts are not otherwise
masked globally or modularly. This bit is cleared by hardware by a CPU read (either the UserCore
or the DSPCore) of the AD4 output register. The ABF4 and ABF5 flags are set in the same clock
cycle.