Rainbow Electronics MAXQ3108 - Manual (Page 34)

MAXQ3108
Low-Power, Dual-Core Microcontroller
34 ______________________________________________________________________________________
Special Function Register Bit Descriptions (continued)
PI2 (05h, 02h) Port 2 Input Register
Initialization: The reset value for this register is dependent on the logical states of the pins.
Read/Write Access: Unrestricted read-only.
PI2.[6:0]:
Port 2 Input Register Bits 6:0. The PI2 register always reflects the logic state of its pins when read.
Note that each port pin has a weak pullup circuit when functioning as an input and the p-channel
pullup transistor is controlled by its respective PO bits. If the PO bit is set to 1, the weak pullup is
on; if the PO bit is cleared to 0, the weak pullup is off and forces the port pin into three-state.
PI2.7: Reserved Reserved. Reads return 0.
SCON0 (06h, 02h) Serial Port 0 Control Register
Initialization: The serial port control is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
SCON0.0: RI
Receive Interrupt Flag. This bit indicates that a data byte has been received in the serial port
buffer. The bit is set at the end of the 8th bit for mode 0, after the last sample of the incoming stop
bit for mode 1 subject to the value of the SM2 bit, or after the last sample of RB8 for modes 2 and
3. This bit must be cleared by software once set.
SCON0.1: TI
Transmit Interrupt Flag. This bit indicates that the data in the serial-port data buffer has been
completely shifted out. It is set at the end of the last data bit for all modes of operation and must
be cleared by software once set.
SCON0.2: RB8
9th Received Bit State. This bit identifies the state of the 9th bit of received data in serial port
modes 2 and 3. When SM2 is 0, it is the state of the stop bit in mode 1. This bit has no meaning in
mode 0.
SCON0.3: TB8
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial port
modes 2 and 3.
SCON0.4: REN
Receive Enable
REN_0 = 0: Serial port 0 receiver disabled.
REN_0 = 1: Serial port 0 receiver enabled for modes 1, 2 and 3. Initiate synchronous reception for
mode 0.
SCON0.5: SM2
Serial Port Mode Bit 2. Setting this bit in mode 1 ignores reception if an invalid stop bit is
detected. Setting this bit in mode 2 or 3 enables multiprocessor communications, and prevents the
RI bit from being set and the interrupt from being asserted if the 9th bit received is 0. This bit is
also used to support mode 0 for clock selection.
SM2 = 0: clock is divided by 12
SM2 = 1: clock is divided by 4
SCON0.6: SM1 Serial Port 0 Mode Bit 1