Rainbow Electronics MAXQ3108 - Manual (Page 25)

MAXQ3108
Low-Power, Dual-Core Microcontroller
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Special Function Register Bit Descriptions (continued)
EIES1 (0Bh, 01h) External Interrupt Edge Select 1 Register
Initialization: EIES1 is cleared to 00h on all forms of reset.
Read/Write Access: Unrestricted read/write.
EIES1.[3:0]: IT[11:8]
External Interrupt Edge Select Bits 11:8
ITx = 0: External interrupt x is positive-edge triggered.
ITx = 1: External interrupt x is negative-edge triggered.
EIES1.[7:4]: Reserved Reserved. Reads return 0.
SVM (0Ch, 01h) Supply Voltage Monitor Register (16-Bit Register)
Initialization: This register is set to 0700h on all forms of reset.
Read/Write Access: Unrestricted read/write except SVMRDY and SVMTH. The supply voltage monitor ready (SVMRDY)
bit is set and cleared by hardware only. SVMTH can only be written to when the supply voltage
monitor is disabled (SVMEN = 0).
SVM.0: SVMEN
Supply Voltage Monitor Enable. Setting this bit to 1 enables the monitoring of supply voltage
according to SVMTH settings. Clearing this bit to 0 disables the supply voltage monitoring
circuitry.
SVM.1: SVMRDY
Supply Voltage Monitor Ready. This bit is set to 1 to indicate that the supply voltage monitor is
ready for use. This bit is cleared to 0 when SVMEN = 0 or on entrance to stop mode if SVMSTOP = 0.
SVM.2: SVMIE
Supply Voltage Monitor Interrupt Enable. Setting this bit to 1 generates an interrupt to the CPU
when SVMI is set to 1. Clearing this bit to 0 disables the interrupt from generating.
SVM.3: SVMI
Supply Voltage Monitor Interrupt. This bit is set to 1 when the supply voltage falls below the set
point defined by SVTH. Clearing this bit to 0 clears the interrupt. However, if the supply voltage is
still below the set point, this flag is set again. Setting this bit to 1 causes an interrupt to the CPU
when SVMIE = 1.
SVM.4: SVMSTOP
Supply Voltage Monitor Stop Mode Enable. Setting this bit to 1 enables the supply voltage monitor
circuit to operate during stop mode if SVMEN = 1. Clearing this bit to 0 disables the supply voltage
monitor when stop mode is enabled.
SVM.[7:5]: Reserved Reserved. Reads return 0.
SVM.[11:8]: SVTH[3:0]
Supply Voltage Threshold Bits [3:0]. These bits are used to select a user-defined supply voltage
threshold under which an interrupt is generated to the CPU if enabled. The level can be adjusted
from 2.0V to 3.5V in a 0.1V increment. The supply voltage monitor is enabled by setting SVMEN =
1. The default value is 07h (2.7V).
Supply Voltage Monitor Threshold = 2.0V + SVMTH[3:0] x 0.1V
Note that the SVTH bits can only be modified when SVMEN = 0. Writing to these bits is ignored if
SVMEN = 1.
SVM.[15:12]: Reserved Reserved. Reads return 0.