Texas Instruments TSB12LV26 - Manual (Page 9)

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List of Tables
Table Title Page
2–1 Signals Sorted by Terminal Number 2–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Signal Names Sorted Alphanumerically to Terminal Number 2–3 . . . . . . . . . .
2–3 Power Supply Terminals 2–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 PCI System Terminals 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 PCI Address and Data Terminals 2–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 PCI Interface Control Terminals 2–6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 IEEE 1394 PHY/Link Terminals 2–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Miscellaneous Terminals 2–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Bit Field Access Tag Descriptions 3–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI Configuration Register Map 3–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Command Register Description 3–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 Status Register Description 3–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Class Code and Revision ID Register Description 3–6 . . . . . . . . . . . . . . . . . . .
3–6 Latency Timer and Class Cache Line Size Register Description 3–6 . . . . . . .
3–7 Header Type and BIST Register Description 3–7 . . . . . . . . . . . . . . . . . . . . . . . .
3–8 OHCI Base Address Register Description 3–7 . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 Subsystem Identification Register Description 3–8 . . . . . . . . . . . . . . . . . . . . . .
3–10 Interrupt Line and Pin Register Description 3–9 . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 MIN_GNT and MAX_LAT Register Description 3–10 . . . . . . . . . . . . . . . . . . . . .
3–12 OHCI Control Register Description 3–10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Capability ID and Next Item Pointer Register Description 3–11 . . . . . . . . . . . . .
3–14 Power Management Capabilities Register Description 3–12 . . . . . . . . . . . . . . .
3–15 Power Management Control and Status Register Description 3–13 . . . . . . . . .
3–16 Power Management Extension Register Description 3–13 . . . . . . . . . . . . . . . . .
3–17 Miscellaneous Configuration Register 3–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Link Enhancement Control Register Description 3–15 . . . . . . . . . . . . . . . . . . . .
3–19 Subsystem Access Register Description 3–16 . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 GPIO Control Register Description 3–17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 OHCI Register Map 4–1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 OHCI Version Register Description 4–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 GUID ROM Register Description 4–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Asynchronous Transmit Retries Register Description 4–6 . . . . . . . . . . . . . . . .
4–5 CSR Control Register Description 4–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Configuration ROM Header Register Description 4–8 . . . . . . . . . . . . . . . . . . . .
4–7 Bus Options Register Description 4–9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Configuration ROM Mapping Register Description 4–11 . . . . . . . . . . . . . . . . . . .
4–9 Posted Write Address High Register Description 4–12 . . . . . . . . . . . . . . . . . . . .