18 power management control and status register, 19 power management extension register – Texas Instruments TSB12LV26 User Manual
Page 33
3–13
3.18 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management
function. This register is not affected by the internally generated reset caused by the transition from the D3
hot
to D0
state. See Table 3–15 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Power management control and status
Type
RC
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Power management control and status
Type:
Read/Clear, Read/Write, Read-only
Offset:
48h
Default:
0000h
Table 3–15. Power Management Control and Status Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_STS
RC
This bit is set when the TSB12LV26 would normally be asserting the PME signal, independent of the
state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, and this also clears the PCI_PME
signal driven by the TSB12LV26. Writing a 0 to this bit has no effect.
14–9
DYN_CTRL
R
Dynamic data control. This field returns 0s when read since the TSB12LV26 does not report dynamic
data.
8
PME_ENB
R/W
PCI_PME enable. This bit enables the function to assert PCI_PME. If this bit is cleared, then assertion
of PCI_PME is disabled.
7–5
RSVD
R
Reserved. Bits 7–5 return 0s when read.
4
DYN_DATA
R
Dynamic data. This bit returns 0 when read since the TSB12LV26 does not report dynamic data.
3–2
RSVD
R
Reserved. Bits 3–2 return 0s when read.
1–0
PWR_STATE
R/W
Power state. This 2-bit field is used to set the TSB12LV26 device power state and is encoded as
follows:
00 = Current power state is D0
01 = Current power state is D1
10 = Current power state is D2
11 = Current power state is D3
3.19 Power Management Extension Register
The power management extension register provides extended power management features not applicable to the
TSB12LV26, thus it is read-only and returns 0s when read. See Table 3–16 for a complete description of the register
contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Power management extension
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Power management extension
Type:
Read-only
Offset:
4Ah
Default:
0000h
Table 3–16. Power Management Extension Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15–8
PM_DATA
R
Power management data. This field returns 00h when read since the TSB12LV26 does not report
dynamic data.
7–0
PMCSR_BSE
R
Power management CSR – bridge support extensions. This field returns 00h when read since the
TSB12LV26 does not provide P2P bridging.