20 miscellaneous configuration register – Texas Instruments TSB12LV26 User Manual
Page 34
3–14
3.20 Miscellaneous Configuration Register
The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–17 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Miscellaneous configuration
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Miscellaneous configuration
Type
R/W
R
R/W
R
R
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Register:
Miscellaneous configuration
Type:
Read/Write, Read-only
Offset:
F0h
Default:
0000 2400h
Table 3–17. Miscellaneous Configuration Register
BIT
FIELD NAME
TYPE
DESCRIPTION
31–16
RSVD
R
Reserved. Bits 31–16 return 0s when read.
15
PME_D3COLD
R/W
PCI_PME support from D3cold. This bit is used to program bit 15 (PME_D3COLD) in the power
management capabilities register (offset 46h, see Section 3.17).
14
RSVD
R
Reserved. Bit 14 returns 0 when read.
13
PME_SUPPORT_D2
R/W
PCI_PME support. This bit is used to program bit 13 (PME_SUPPORT_D2) in the power
management capabilities register (offset 46h, see Section 3.17). If wake from the D2 power state
implemented in the TSB12LV26 is not desired, then this bit may be cleared to indicate to power
management software that wake-up from D2 is not supported.
12–11
RSVD
R
Reserved. Bits 12–11 return 0s when read.
10
D2_SUPPORT
R/W
D2 support. This bit is used to program bit 10 (D2_SUPPORT) in the power management
capabilities register (offset 46h, see Section 3.17). If the D2 power state implemented in the
TSB12LV26 is not desired, then this bit may be cleared to indicate to power management software
that D2 is not supported.
9–5
RSVD
R
Reserved. Bits 9–5 return 0s when read.
4
DIS_TGT_ABT
R/W
This bit defaults to 0, which provides OHCI-Lynx compatible target abort signaling. When this bit is
set to 1, it enables the no-target-abort mode, in which the TSB12LV26 returns indeterminate data
instead of signaling target abort.
The link is divided into the PCI_CLK and SCLK domains. If software tries to access registers in the
link that are not active because the SCLK is disabled, a target abort is issued by the link. On some
systems this can cause a problem resulting in a fatal system error. Enabling this bit allows the link
to respond to these types of requests by returning FFh.
It is recommended that this bit be set to 1.
3
GP2IIC
R/W
When this bit is set to 1, the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA,
respectively. The GPIO3 and GPIO2 terminals are also placed in a high impedance state.
2
DISABLE_SCLKGATE
R/W
When this bit is set to 1, the internal SCLK runs identically with the chip input. This bit is a test
feature only and should be cleared to 0 (all applications).
1
DISABLE_PCIGATE
R/W
When this bit is set, the internal PCI clock runs identically with the chip input. This bit is a test
feature only and should be cleared to 0 (all applications).
0
KEEP_PCLK
R/W
When this bit is set to 1, the PCI clock is always kept running through the PCI_CLKRUN protocol.
When this bit is cleared, the PCI clock may be stopped using PCI_CLKRUN.