Texas Instruments TSB12LV26 - Manual (Page 56)

4–18
Table 4–14. Interrupt Event Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
17 busReset RSCU Indicates that the PHY chip has entered bus reset mode.
16 selfIDcomplete RSCU
A selfID packet stream has been received. It is generated at the end of the bus initialization process.
This bit is turned off simultaneously when bit 17 (busReset) is turned on.
15–10 RSVD R Reserved. Bits 15–10 return 0s when read.
9 lockRespErr RSCU
Indicates that the TSB12LV26 sent a lock response for a lock request to a serial bus register, but did
not receive an ack_complete.
8 postedWriteErr RSCU
Indicates that a host bus error occurred while the TSB12LV26 was trying to write a 1394 write request,
which had already been given an ack_complete, into system memory.
7 isochRx RU
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event, it is the logical OR of all bits in the isochronous
receive interrupt event (OHCI offset A0h/A4h, see Section 4.25) and isochronous receive interrupt
mask (OHCI offset A8h/ACh, see Section 4.26) registers. The isochronous receive interrupt event
register indicates which contexts have interrupted.
6 isochTx RU
Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated an interrupt. This is not a latched event, it is the logical OR of all bits in the isochronous
transmit interrupt event (OHCI offset 90h/94h, see Section 4.23) and isochronous transmit interrupt
mask (OHCI offset 98h/9Ch, see Section 4.24) registers. The isochronous transmit interrupt event
register indicates which contexts have interrupted.
5 RSPkt RSCU
Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor xferStatus and resCount fields have been updated.
4 RQPkt RSCU
Indicates that a packet was sent to an asynchronous receive request context buffer and the
descriptor xferStatus and resCount fields have been updated.
3 ARRS RSCU
Async receive response DMA interrupt. This bit is conditionally set upon completion of an ARRS DMA
context command descriptor.
2 ARRQ RSCU
Async receive request DMA interrupt. This bit is conditionally set upon completion of an ARRQ DMA
context command descriptor.
1 respTxComplete RSCU
Asynchronous response transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRS DMA command.
0 reqTxComplete RSCU
Asynchronous request transmit DMA interrupt. This bit is conditionally set upon completion of an
ATRQ DMA command.