Texas Instruments TSB12LV26 User Manual
Page 22
3–2
Internal
Registers
ISO Transmit
Contexts
Async Transmit
Contexts
Physical DMA
& Response
PCI
Target
SM
PHY
Register
Access
& Status
Monitor
Central
Arbiter
&
PCI
Initiator
SM
Cycle Start
Generator &
Cycle Monitor
Synthesized
Bus Reset
Receive
FIFO
Link
Transmit
Link
Receive
PCI
Host
Bus
Interface
Resp
Timeout
Request
Filters
General
Request Receive
Async Response
Receive
ISO Receive
Contexts
OHCI PCI Power
Mgmt & CLKRUN
Transmit
FIFO
Receive
Acknowledge
Serial
ROM
GPIOs
CRC
PHY /
Link
Interface
MISC
Interface
Figure 3–1. TSB12LV26 Block Diagram
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