Texas Instruments TSB12LV26 - Manual (Page 50)

4–12
4.14 Posted Write Address High Register
The posted write address high register is used to communicate error information if a write request is posted and an
error occurs while writing the posted data packet. See Table 4–9 for a complete description of the register contents.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Posted write address high
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Posted write address high
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default X X X X X X X X X X X X X X X X
Register: Posted write address high
Type: Read/Update
Offset: 3Ch
Default: XXXX XXXXh
Table 4–9. Posted Write Address High Register Description
BIT FIELD NAME TYPE DESCRIPTION
31–16 sourceID RU
This field is the bus and node number of the node that issued the write request that failed. Bits 31–22
are the 10-bit bus number and bits 21–16 are the 6-bit node number.
15–0 offsetHi RU The upper 16 bits of the 1394 destination offset of the write request that failed.
4.15 Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers. The
TSB12LV26 does not implement Texas Instruments unique behavior with regards to OHCI. Thus, this register is
read-only and returns 0s when read.
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Vendor ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Vendor ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Vendor ID
Type: Read-only
Offset: 40h
Default: 0000 0000h