Texas Instruments TSB12LV26 - Manual (Page 78)

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4.42 Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first descriptor
block that the TSB12LV26 accesses when software enables an isochronous receive context by setting the
isochronous receive context control register (see Section 4.41) bit 15 (run). The n value in the following register
addresses indicates the context number (n = 0, 1, 2, 3).
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Isochronous receive context command pointer
Type R R R R R R R R R R R R R R R R
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Isochronous receive context command pointer
Type R R R R R R R R R R R R R R R R
Default X X X X X X X X X X X X X X X X
Register: Isochronous receive context command pointer
Type: Read-only
Offset: 40Ch + (32 * n)
Default: XXXX XXXXh