Texas Instruments TSB12LV26 - Manual (Page 39)

4–1
4 OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a
2-Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see
Section 3.9). These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function.
This section provides the register interface and bit descriptions. There are several set/clear register pairs in this
programming model, which are implemented to solve various issues with typical read-modify-write control registers.
There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 4–1 for an illustration.
A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a 0 bit leaves the
corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register
to be cleared, while a 0 bit leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively.
However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt
event register is an example of this behavior.
Table 4–1. OHCI Register Map
DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET
— OHCI version Version 00h
GUID ROM GUID_ROM 04h
Asynchronous transmit retries ATRetries 08h
CSR data CSRData 0Ch
CSR compare data CSRCompareData 10h
CSR control CSRControl 14h
Configuration ROM header ConfigROMhdr 18h
Bus identification BusID 1Ch
Bus options BusOptions 20h
GUID high GUIDHi 24h
GUID low GUIDLo 28h
Reserved — 2Ch–30h
Configuration ROM map ConfigROMmap 34h
Posted write address low PostedWriteAddressLo 38h
Posted write address high PostedWriteAddressHi 3Ch
Vendor identification VendorID 40h–4Ch
Host controller control
HCControlSet 50h
Host controller control
HCControlClr 54h
Reserved — 58h–5Ch