Texas Instruments TSB12LV26 - Manual (Page 83)

6–1
6 Serial ROM Interface
The TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI
configuration registers through a serial ROM. The TSB12LV26 communicates with the serial ROM via the 2-wire serial
interface.
After power-up the serial interface initializes the locations listed in Table 6–1. While the TSB12LV26 is accessing the
serial ROM, all incoming PCI slave accesses are terminated with retry status. Table 6–2 shows the serial ROM
memory map required for initializing the TSB12LV26 registers.
Table 6–1. Registers and Bits Loadable through Serial ROM
ROM OFFSET OHCI/PCI OFFSET REGISTER
BITS LOADED
FROM ROM
00h PCI register (3Eh) PCI maximum latency, PCI minimum grant 15–0
01h PCI register (2Dh) PCI vendor ID 15–0
03h PCI register (2Ch) PCI subsystem ID 15–0
05h (bit 6) OHCI register (50h) Host controller control register 23
05h PCI register (F4h) Link enhancements control register 7, 2, 1
06h – 0Ah OHCI register (24h) GUID high 31–0
0Bh – 0Eh OHCI register(28h) GUID low 31–0
10h PCI register (F4h) Link enhancements control register 13, 12
12h PCI register (F0h) PCI miscellaneous register 15, 13, 10
13h PCI register (40h) PCI OHCI register 0