Texas Instruments TSB12LV26 - Manual (Page 10)

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4–10 Host Controller Control Register Description 4–13 . . . . . . . . . . . . . . . . . . . . . . . .
4–11 Self-ID Count Register Description 4–14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–12 Isochronous Receive Channel Mask High Register Description 4–15 . . . . . . .
4–13 Isochronous Receive Channel Mask Low Register Description 4–16 . . . . . . . .
4–14 Interrupt Event Register Description 4–17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–15 Interrupt Mask Register Description 4–19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–16 Isochronous Transmit Interrupt Event Register Description 4–20 . . . . . . . . . . .
4–17 Isochronous Receive Interrupt Event Register Description 4–22 . . . . . . . . . . .
4–18 Fairness Control Register Description 4–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–19 Link Control Register Description 4–24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–20 Node Identification Register Description 4–25 . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–21 PHY Control Register Description 4–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–22 Isochronous Cycle Timer Register Description 4–27 . . . . . . . . . . . . . . . . . . . . . .
4–23 Asynchronous Request Filter High Register Description 4–28 . . . . . . . . . . . . .
4–24 Asynchronous Request Filter Low Register Description 4–30 . . . . . . . . . . . . . .
4–25 Physical Request Filter High Register Description 4–31 . . . . . . . . . . . . . . . . . . .
4–26 Physical Request Filter Low Register Description 4–33 . . . . . . . . . . . . . . . . . . .
4–27 Asynchronous Context Control Register Description 4–35 . . . . . . . . . . . . . . . . .
4–28 Asynchronous Context Command Pointer Register Description 4–36 . . . . . . .
4–29 Isochronous Transmit Context Control Register Description 4–37 . . . . . . . . . .
4–30 Isochronous Receive Context Control Register Description 4–38 . . . . . . . . . . .
4–31 Isochronous Receive Context Match Register Description 4–41 . . . . . . . . . . . .
6–1 Registers and Bits Loadable through Serial ROM 6–1 . . . . . . . . . . . . . . . . . . .
6–2 Serial ROM Map 6–2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .