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7 configuration rom header register, 8 bus identification register – Texas Instruments TSB12LV26 User Manual

Page 46

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4–8

4.7

Configuration ROM Header Register

The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset
FFFF F000 0400h. See Table 4–6 for a complete description of the register contents.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Configuration ROM header

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Configuration ROM header

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Register:

Configuration ROM header

Type:

Read/Write

Offset:

18h

Default:

0000 XXXXh

Table 4–6. Configuration ROM Header Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–24

info_length

R/W

IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control
register (OHCI offset 50h/54h, see Section 4.16) is set.

23–16

crc_length

R/W

IEEE 1394 bus management field. Must be valid when bit 17 (linkEnable) of the host controller control
register (OHCI offset 50h/54h, see Section 4.16) is set.

15–0

rom_crc_value

R/W

IEEE 1394 bus management field. Must be valid at any time bit 17 (linkEnable) of the host controller
control register (OHCI offset 50h/54h, see Section 4.16) is set. The reset value is undefined if no serial
ROM is present. If a serial ROM is present, then this field is loaded from the serial ROM.

4.8

Bus Identification Register

The bus identification register externally maps to the first quadlet in the Bus_Info_Block, and contains the constant
3133 3934h, which is the ASCII value of 1394.

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Name

Bus identification

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Default

0

0

1

1

0

0

0

1

0

0

1

1

0

0

1

1

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Bus identification

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Default

0

0

1

1

1

0

0

1

0

0

1

1

0

1

0

0

Register:

Bus identification

Type:

Read-only

Offset:

1Ch

Default:

3133 3934h