16 host controller control register – Texas Instruments TSB12LV26 User Manual
Page 51
4–13
4.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the TSB12LV26. See Table 4–10 for
a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Host controller control
Type
R
RSC
R
R
R
R
R
R
RC
RSC
R
R
RSC
RSC
RSC
RSCU
Default
0
X
0
0
0
0
0
0
0
0
0
0
0
X
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Host controller control
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Host controller control
Type:
Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read-only
Offset:
50h
set register
54h
clear register
Default:
X00X 0000h
Table 4–10. Host Controller Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
RSVD
R
Reserved. Bit 31 returns 0 when read.
30
noByteSwapData
RSC
This bit is used to control whether physical accesses to locations outside the TSB12LV26 itself as
well as any other DMA data accesses should be swapped.
29–24
RSVD
R
Reserved. Bits 29–24 return 0s when read.
23
programPhyEnable
RC
This bit informs upper level software that lower level software has consistently configured the
P1394a enhancements in the Link and PHY. When this bit is 1, generic software such as the OHCI
driver is responsible for configuring P1394a enhancements in the PHY and bit 22
(aPhyEnhanceEnable) in the TSB12LV26. When this bit is 0, the generic software may not modify
the P1394a enhancements in the TSB12LV26 or PHY and cannot interpret the setting of bit 22
(aPhyEnhanceEnable). This bit is initialized from serial EEPROM.
22
aPhyEnhanceEnable
RSC
When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set this bit to
use all P1394a enhancements. When bit 23 (programPhyEnable) is set to 0, the software does
not change PHY enhancements or this bit.
21–20
RSVD
R
Reserved. Bits 21–20 return 0s when read.
19
LPS
RSC
This bit is used to control the link power status. Software must set this bit to 1 to permit link-PHY
communication. A 0 prevents link-PHY communication.
18
postedWriteEnable
RSC
This bit is used to enable (1) or disable (0) posted writes. Software should change this bit only
when bit 17 (linkEnable) is 0.
17
linkEnable
RSC
This bit is cleared to 0 by either a hardware or software reset. Software must set this bit to 1 when
the system is ready to begin operation and then force a bus reset. This bit is necessary to keep
other nodes from sending transactions before the local system is ready. When this bit is cleared,
the TSB12LV26 is logically and immediately disconnected from the 1394 bus, no packets are
received or processed nor are packets transmitted.
16
SoftReset
RSCU
When this bit is set, all TSB12LV26 states are reset, all FIFOs are flushed, and all OHCI registers
are set to their hardware reset values unless otherwise specified. PCI registers are not affected by
this bit. This bit remains set while the soft reset is in progress and reverts back to 0 when the reset
has completed.
15–0
RSVD
R
Reserved. Bits 15–0 return 0s when read.