Texas Instruments MSP50C614 - Manual (Page 407)

Architecture
B-5 MSP50C604 Preliminary Data
B.3.4 Slave Mode Operation
The MSP50C604 is used as a peripheral device in slave mode. A microproces-
sor/microcontroller controls the R/WZ, STROBE, INRDY, OUTRDY pins of
MSP50C604 to use it as a slave processor. No special programming is re-
quired to switchthe ’C604 to slave mode. Slave mode is exclusively controlled
by the four pins mentioned above.
B.3.5 Host Write Sequence
1) MSP50C604 signals readiness to receive data by taking INRDY low
2) Host takes R/WZ low.
3) Host puts 8 bit data on port C pins PC
0
–PC
7
.
4) Host takes STROBE low.
5) On rising edge of STROBE, data latched into port A, INRDY goes high,
rising edge interrupt (INT3) is activated.
6) When input latch is read, INRDY goes low to restart cycle
B.3.6 Host Read Sequence
1) MSP50C604 signals readiness to receive data by taking OUTRDY low.
2) Host takes R/WZ high.
3) Host takes STROBE low.
4) Data port C sets as output by MSP50C604.
5) MSP50C604 program has already written 8 bit data into IO port C.
6) Host reads data from port pins PC
0
–PC
7
.
7) Host takes STROBE high.
8) On rising edge of STROBE, OUTRDY goes high, data port goes 3-state
and falling edge interrupt (INT4) is activated.
9) When MSP50C604 writes to the output latch, OUTRDY goes low to restart
cycle.