Texas Instruments MSP50C614 - Manual (Page 396)

Introduction
A-2
A.1 Introduction
MSP50C605 is a spin off of the core processor MSP50C614. It uses three IO
ports of MSP50C614 and maps a 1.835 Mbits of internal ROM. Using a 1 kbps
MELP algorithm, the C605 can provide over 30 minutes of uninterrupted
speech. There is no Port A and Port B control register in MSP50C605. Port
DRD is read only, and Port DRP and DRA are write only. Apart from the addi-
tional ROM and corresponding IO port changes, all other functionality of the
processor is similar to MSP50C614. The mapping is as follows:
Port Name IO Location MSP50C614 MSP50C605
Port A 0x00 General purpose bit configurable IO Data ROM data (DRD)
Port B 0x08 General purpose bit configurable IO Data ROM page (DRP)
Port G 0x2C General purpose 16 bit output Data ROM address (DRA)
A.2 Features
- 30k word ROM customer program memory
- Approximately 1.835 Mbits data ROM
- 8 MHz uDSP core
- 32 input or output pins
J 24 Pins general-purpose, bit configurable as input or output
J 8 input pins with programmable 100-
Ω
pull-up resistors
- 1 bit comparator with edge-detection interrupt service
(IMPORTANT: Not currently supported)
- PLL clock synthesizer
- Resistor trimmed oscillator or 32 kHz crystal
- 640 word RAM
- PDM DAC w/direct speaker drive (32
Ω
)
- Serial scan port for in-circuit emulation/monitor/test
A.3 Architecture
The MSP50C605 uses the MSP50C614 core, including breakpoint capability.
It has identical instruction sets and uses the same development tool.
MSP50P614 (EPROM device) is used for code development and testing.
MSP50C605 architecture is shown in Figure A–1.