Texas Instruments MSP50C614 - Manual (Page 398)

Architecture
A-4
Figure A–1. MSP50C605 Architecture
Data ROM access
Core
CU Computational Unit
PCU Prog. Counter Unit
Instr. Decoder
TIMER1 PRD1 TIM1
0x3A 0x3B
Clock Control 0x3D
Gen. Control 0x38
RAM 640 x 17 bit
(data) 0x0000 to
0x027F
Power
V PP V DD V SS
F port INPUT
DATA 0x28
8
PF0..7
Data ROM
229,376 x 8 bit
DRA 0x2C
DRD 0x00
DRP 0x08
C port I/0
Control 0x14
DATA 0x10
8
PC0..7
E port I/0
DATA 0x20
8
PE0..7
Initialization
Logic RESET
DAC 0x30
32 Ohm PDM DAC M
DAC P
SYNC
TEST
Scan Interface SCAN IN
SCANOUT
SCANCLK
(EP)ROM 32k x (16 + 1) bit
User ROM 0x0800 to
0x7FEF
INT vectors 0x7FF0 to
0x7FFF
Test–Area 0x0000 to
(reserved) 0x07FF
D port I/0
DATA 0x18
8
PD0..7
Comparator
1 bit: PD5 vs. PD4
+ –
OSC Reference
PLL Filter PLL
OSC OUT
Crystal
Referenced
32.768 kHz
Resistor
Trimmed
32 kHz nominal
OSC IN or
or
Break Point
Emulation
OTP Program
Serial Comm.
Control 0x24
TIMER2 PRD2 TIM2
0x3E 0x3F
Interrupt Processor
FLAG MASK
0x39 0x38
DMAU Data Mem. Addr.
5 5
PGM PULSE
(C605 only)
(P614 only)
(P614 only)
RTOTRIM Register 0x2F
DAC Data/Control
Control Data
0x34 0x30
/
/
/
/
Control 0x1C