Texas Instruments MSP50C614 - Manual (Page 32)

2-2
2.1 Architecture Overview
The core processor in the C614 is a medium performance mixed signal pro-
cessor with enhanced microcontroller features and a limited DSP instruction
set. In addition to its basic multiply/accumulate structure for DSP routines, the
core provides for a very efficient handling of string and bit manipulation. A
unique accumulator-register file provides additional scratch pad memory and
minimizes memory thrashing for many operations. Five different addressing
modes and many short direct references provide enhanced execution and
code efficiency.
The basic elements of the C614 core are shown in Figure 2–1. In addition to
the main computational units, the core’s auxiliary functions include two timers,
an eight-level interrupt processor, a clock generation circuit, a serial scan-port
interface, and a general control register.