Intel CHIPSET 820E User Manual
Intel, 820e chipset
Table of contents
Document Outline
- Title Page
- Contents
- Revision History
- Introduction
- Layout/Routing Guidelines
- General Recommendations
- Component Quadrant Layout
- Intel® 820E Chipset Component Placement
- Core Chipset Routing Recommendations
- Source-Synchronous Strobing
- Differential Clocking/Strobing
- Direct RDRAM* Interface
- AGP 2.0
- AGP Interface Signal Groups
- 1× Timing Domain Routing Guidelines
- 2Ч/4Ч Timing Domain Routing Guidelines
- AGP 2.0 Routing Summary
- AGP Clock Routing
- General AGP Routing Guidelines
- VDDQ Generation and TYPEDET#
- VREF Generation for AGP 2.0 (2× and 4×)
- Compensation
- AGP Pull-Ups
- Motherboard / Add-in Card Interoperability
- AGP Universal Retention Mechanism (RM)
- Hub Interface
- System Bus Design – Pentium® III Processor for the Intel® PGA370 Socket Layout Guidelines
- Additional Host Bus Guidelines
- IDE Interface
- AC’97
- USB
- ISA Support
- I/O APIC Design Recommendation
- SMBus/SMLink Interface
- PCI
- RTC
- SPKR Pin Consideration
- ICH2 PIRQ Routing
- LAN Layout Guidelines
- ICH2 – LAN Interconnect Guidelines
- General LAN Routing Guidelines and Considerations
- Intel® 82562EH Home/PNA* Guidelines
- Intel® 82562ET / Intel® 82562EM Component Guidelines
- Intel® 82562ET/EM Disable Guidelines
- Intel® 82562ET and Intel® 82562EH Components’ Dual-Footprint Guidelines
- ICH2 Decoupling Recommendations
- FWH Flash BIOS Guidelines
- ICH2 Design Checklist
- ICH2 Layout Checklist
- Advanced System Bus Design
- Clocking
- Clock Generation
- Component Placement and Interconnection Layout Requirements
- DRCG Impedance Matching Circuit
- AGP Clock Routing Guidelines
- Clock Routing Guidelines for Intel® PGA370 Designs
- Series Termination Resistors for CK133 Clock Outputs
- Unused Outputs
- Decoupling Recommendation for CK133 and DRCG
- DRCG Frequency Selection and the DRCG+
- System Manufacturing
- System Design Considerations
- Appendix A: Reference Design Schematics (Uniprocessor)